On Tue, Mar 24, 2015 at 10:25 PM, Leo Yan leo.yan@linaro.org wrote:
Add memory barrier for mmio write and read operations, so that it will be much stable for initialization.
Are you sure you don't have the MMU mapping incorrect? These should not be needed with proper mappings.
Looking at the other patches, I would guess you have some ordering problem between SRAM writes and register writes. I'm just guessing as I have no clue what exactly is not stable. You should put barriers where needed rather than wholesale barrier in every register access.
Rob
Signed-off-by: Leo Yan leo.yan@linaro.org
include/lib/mmio.h | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/include/lib/mmio.h b/include/lib/mmio.h index cb37a1c..e43cd93 100644 --- a/include/lib/mmio.h +++ b/include/lib/mmio.h @@ -31,36 +31,52 @@ #ifndef __MMIO_H__ #define __MMIO_H__
+#include <arch_helpers.h> #include <stdint.h>
static inline void mmio_write_8(uintptr_t addr, uint8_t value) {
dsb(); *(volatile uint8_t*)addr = value;}
static inline uint8_t mmio_read_8(uintptr_t addr) {
return *(volatile uint8_t*)addr;
uint8_t val;val = *(volatile uint8_t*)addr;dsb();return val;}
static inline void mmio_write_32(uintptr_t addr, uint32_t value) {
dsb(); *(volatile uint32_t*)addr = value;}
static inline uint32_t mmio_read_32(uintptr_t addr) {
return *(volatile uint32_t*)addr;
uint32_t val;val = *(volatile uint32_t*)addr;dsb();return val;}
static inline void mmio_write_64(uintptr_t addr, uint64_t value) {
dsb(); *(volatile uint64_t*)addr = value;}
static inline uint64_t mmio_read_64(uintptr_t addr) {
return *(volatile uint64_t*)addr;
uint64_t val;val = *(volatile uint64_t*)addr;dsb();return val;}
#endif /* __MMIO_H__ */
1.9.1
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