Dev October 2015

dev@lists.96boards.org

28 participants
15 discussions

[BUG] PSCI patch in HiKey Kernel tree breaks booting

by Lee Jones

Bisected to this commit: commit af016d94f7e50ffd4ca0fe93a22cb07c06f4c4bf (HEAD, refs/bisect/bad) Author: Leo Yan <leo.yan(a)linaro.org> Date: Thu Mar 12 10:23:48 2015 +0800 arm64: dts: enable psci in hikey Enable psci in Hisilicon Hi6220 HiKey board. Signed-off-by: Haojian Zhuang <haojian.zhuang(a)linaro.org> Signed-off-by: Leo Yan <leo.yan(a)linaro.org> diff --git a/arch/arm64/boot/dts/hi6220.dtsi b/arch/arm64/boot/dts/hi6220.dtsi index d3428f4..e15c862 100644 --- a/arch/arm64/boot/dts/hi6220.dtsi +++ b/arch/arm64/boot/dts/hi6220.dtsi @@ -9,6 +9,11 @@ #include <dt-bindings/pinctrl/hisi.h> / { + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -17,8 +22,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x740fff8>; + enable-method = "psci"; clocks = <&clock_acpu HI6220_STUB_ACPU0>; clock-names = "acpu0"; clock-latency = <0>; @@ -36,57 +40,44 @@ compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x740fff8>; - clock-latency = <0>; + enable-method = "psci"; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x740fff8>; - clock-latency = <0>; + enable-method = "psci"; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x740fff8>; - clock-latency = <0>; + enable-method = "psci"; }; cpu4: cpu@4 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x740fff8>; + enable-method = "psci"; clock-latency = <0>; }; cpu5: cpu@5 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x740fff8>; - clock-latency = <0>; + enable-method = "psci"; }; cpu6: cpu@6 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x102>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x740fff8>; - clock-latency = <0>; + enable-method = "psci"; }; cpu7: cpu@7 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; reg = <0x0 0x103>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x740fff8>; - clock-latency = <0>; + enable-method = "psci"; }; cpu-map { @@ -211,7 +202,6 @@ <1 14 0xff08>, <1 11 0xff08>, <1 10 0xff08>; - clock-frequency = <1200000>; }; reboot { -- Lee Jones Linaro ST Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog

9 years, 2 months

HiKey U-Boot port

by Peter Griffin

Hi folks, For fun I've done a minimal U-Boot port for the HiKey board, I thought I'd post it here in case anyone else is interested. This work is based on top of Linus Walleij Juno port. The code can be found here: - ssh://git@git.linaro.org:/people/peter.griffin/u-boot Currently the port supports: - 1) Serial 2) eMMC (although only basic read testing) 3) USB (ASIX usb networking works, no mass storage) 4) GPIO So you have ATF -> u-boot -> kernel / your_own_rtos The main "useful" thing I suppose is the ability to quickly tftp kernels etc into DDR over the network. Obviously the ability to toggle the LEDs in u-boot is also something to amuse yourself with. Pre-built binaries can be found here: - http://people.linaro.org/~peter.griffin/hikey/hikey-u-boot-release_r1/ NB: These are built with the latest PSCI enabled ATF, so you also need to use the corresponding PSCI enabled kernel to get all 8 cores. The readme on how to replicate everything from source can be found here: - http://people.linaro.org/~peter.griffin/hikey/hikey-u-boot-release_r1/u-boo… . Any patches please send them along to me, one obvious missing feature is sdhci support. That doesn't look very hard to get going, as long as we can get the IP clocked and out of reset (and would be significantly easier if the published datasheet documented the registers...). Have Fun! regards, Peter. p.s. serial trace below debug EMMC boot: print init OK debug EMMC boot: send RST_N . debug EMMC boot: start eMMC boot...... load fastboot1! Switch to aarch64 mode. CPU0 executes at 0xf9801000! NOTICE: Booting Trusted Firmware NOTICE: BL1: v1.1(release):9a97502 NOTICE: BL1: Built : 08:13:36, Mar 10 2015 NOTICE: succeed to init lpddr3 rank0 dram phy INFO: lpddr3_freq_init, set ddrc 533mhz INFO: init ddr3 rank0 in 533MHz INFO: ddr3 rank1 init pass in 533MHz INFO: Elpida DDR NOTICE: BL1: Booting BL2 NOTICE: BL2: v1.1(debug):9a97502 NOTICE: BL2: Built : 10:22:35, Mar 17 2015 INFO: BL2: Loading BL3-1 INFO: Using FIP INFO: Loading file 'bl31.bin' at address 0xf9858000 INFO: File 'bl31.bin' loaded: 0xf9858000 - 0xf985f010 INFO: BL2: Loading BL3-3 INFO: Using FIP INFO: Loading file 'bl33.bin' at address 0x37000000 INFO: File 'bl33.bin' loaded: 0x37000000 - 0x3703db38 NOTICE: BL1: Booting BL3-1 NOTICE: BL3-1: v1.1(debug):9a97502 NOTICE: BL3-1: Built : 10:22:38, Mar 17 2015 INFO: BL3-1: Initializing runtime services INFO: BL3-1: Preparing for EL3 exit to normal world INFO: BL3-1: Next image address = 0x37000000 INFO: BL3-1: Next image spsr = 0x3c9 U-Boot 2015.04-rc1-00010-g49ec0dd (Mar 17 2015 - 10:11:00) hikey_aemv8a DRAM: 1 GiB MMC: HiKey DWMMC: 0 Using default environment In: serial Out: serial Err: serial Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 HiKey64# usb start starting USB... USB0: Core Release: 3.00a scanning bus 0 for devices... 3 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... Warning: asx0 using MAC address from net device 1 Ethernet Device(s) found HiKey64# HiKey64# setenv ipaddr 192.168.0.200 HiKey64# HiKey64# setenv serverip 192.168.0.10 HiKey64# HiKey64# tftpboot 0x10000000 Image Using asx0 device TFTP from server 192.168.0.10; our IP address is 192.168.0.200 Filename 'Image'. Load address: 0x10000000 Loading: ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ######################################################T ########### ################################################################# ################################################################# ################################################################# ################################################################# ################################################################# ############################################## 238.3 KiB/s done Bytes transferred = 12214232 (ba5fd8 hex) HiKey64# tftpboot 0x13000000 hi6220-hikey.dtb Using asx0 device TFTP from server 192.168.0.10; our IP address is 192.168.0.200 Filename 'hi6220-hikey.dtb'. Load address: 0x13000000 Loading: ################# 237.3 KiB/s done Bytes transferred = 85319 (14d47 hex) HiKey64# ï¿½ooti 0x10000000 - 0x13000000 Unknown command 'ï¿½ooti' - try 'help' HiKey64# Unknown command 'ï¿½ooti' - try 'help' HiKey64# booti 0x10000000 - 0x13000000 ## Flattened Device Tree blob at 13000000 Booting using the fdt blob at 0x13000000 Using Device Tree in place at 0000000013000000, end 0000000013017d46 Starting kernel ... [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Initializing cgroup subsys cpuacct [ 0.000000] Linux version 3.18.0+ (griffinp@griffinp-ThinkPad-X1-Carbon-2nd) (gcc version 4.9.2 20140904 (prerelease) (crosstool-NG linaro-1.13.1-4.9-2014.09 - Linaro GCC 4.9-2014.09) ) #5 SMP PREEMPT Tue Mar 17 08:21:27 GMT 2015 [ 0.000000] CPU: AArch64 Processor [410fd033] revision 3 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: UEFI not found. [ 0.000000] cma: Reserved 16 MiB at 0x000000003f000000 [ 0.000000] On node 0 totalpages: 262144 [ 0.000000] DMA zone: 3584 pages used for memmap [ 0.000000] DMA zone: 0 pages reserved [ 0.000000] DMA zone: 262144 pages, LIFO batch:31 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] PERCPU: Embedded 14 pages/cpu @ffffffc03eefc000 s18688 r8192 d30464 u57344 [ 0.000000] pcpu-alloc: s18688 r8192 d30464 u57344 alloc=14*4096 [ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 258560 [ 0.000000] Kernel command line: console=ttyAMA0,115200n8 root=/dev/sda1 rw earlyprintk=pl011,0x7ff80000 debug user_debug=31 loglevel=9 [ 0.000000] log_buf_len individual max cpu contribution: 4096 bytes [ 0.000000] log_buf_len total cpu_extra contributions: 28672 bytes [ 0.000000] log_buf_len min size: 16384 bytes [ 0.000000] log_buf_len: 65536 bytes [ 0.000000] early log buf free: 14752(90%) [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes) [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes) [ 0.000000] Memory: 994464K/1048576K available (7777K kernel code, 651K rwdata, 3116K rodata, 376K init, 492K bss, 54112K reserved) [ 0.000000] Virtual kernel memory layout: [ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbdffff0000 ( 247 GB) [ 0.000000] vmemmap : 0xffffffbe00000000 - 0xffffffbfc0000000 ( 7 GB maximum) [ 0.000000] 0xffffffbe00000000 - 0xffffffbe00e00000 ( 14 MB actual) [ 0.000000] PCI I/O : 0xffffffbffa000000 - 0xffffffbffb000000 ( 16 MB) [ 0.000000] fixed : 0xffffffbffbdfe000 - 0xffffffbffbdff000 ( 4 KB) [ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB) [ 0.000000] memory : 0xffffffc000000000 - 0xffffffc040000000 ( 1024 MB) [ 0.000000] .init : 0xffffffc000b25000 - 0xffffffc000b83000 ( 376 KB) [ 0.000000] .text : 0xffffffc000080000 - 0xffffffc000b24564 ( 10898 KB) [ 0.000000] .data : 0xffffffc000b83000 - 0xffffffc000c25fd8 ( 652 KB) [ 0.000000] Preemptible hierarchical RCU implementation. [ 0.000000] RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=8. [ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8 [ 0.000000] NR_IRQS:64 nr_irqs:64 16 [ 0.000000] hisi_clk_register_stub: base=0xffffff8000002af4, comm_base=0xffffff8000008000 [ 0.000000] hisi_clk_init: base ffffff800000a000 [ 0.000000] hisi_clk_init: base ffffff800000c000 [ 0.000000] hisi_clk_init: base ffffff800000e000 [ 0.000000] hisi_clk_init: base ffffff8000010000 [ 0.000000] Architected cp15 timer(s) running at 1.20MHz (phys). [ 0.000005] sched_clock: 56 bits at 1200kHz, resolution 833ns, wraps every 3579139414016ns [ 0.000422] Console: colour dummy device 80x25 [ 0.001558] allocated 4194304 bytes of page_cgroup [ 0.001562] please try 'cgroup_disable=memory' option if you don't want memory cgroups [ 0.001575] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.40 BogoMIPS (lpj=12000) [ 0.001584] pid_max: default: 32768 minimum: 301 [ 0.001694] Security Framework initialized [ 0.001710] SELinux: Initializing. [ 0.001737] SELinux: Starting in permissive mode [ 0.001787] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes) [ 0.001794] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes) [ 0.002309] Initializing cgroup subsys memory [ 0.002333] Initializing cgroup subsys freezer [ 0.002343] Initializing cgroup subsys hugetlb [ 0.002352] Initializing cgroup subsys debug [ 0.004190] /cpus/cpu@0: Missing clock-frequency property [ 0.004230] /cpus/cpu@1: Missing clock-frequency property [ 0.004269] /cpus/cpu@2: Missing clock-frequency property [ 0.004309] /cpus/cpu@3: Missing clock-frequency property [ 0.004350] /cpus/cpu@4: Missing clock-frequency property [ 0.004393] /cpus/cpu@5: Missing clock-frequency property [ 0.004437] /cpus/cpu@6: Missing clock-frequency property [ 0.004481] /cpus/cpu@7: Missing clock-frequency property [ 0.004517] hw perfevents: enabled with arm/armv8-pmuv3 PMU driver, 7 counters available [ 0.004545] EFI services will not be available. [ 0.079936] CPU1: Booted secondary processor [ 0.079944] Detected VIPT I-cache on CPU1 [ 0.099879] CPU2: Booted secondary processor [ 0.099882] Detected VIPT I-cache on CPU2 [ 0.119886] CPU3: Booted secondary processor [ 0.119889] Detected VIPT I-cache on CPU3 [ 0.139922] CPU4: Booted secondary processor [ 0.139929] Detected VIPT I-cache on CPU4 [ 0.159920] CPU5: Booted secondary processor [ 0.159924] Detected VIPT I-cache on CPU5 [ 0.179929] CPU6: Booted secondary processor [ 0.179932] Detected VIPT I-cache on CPU6 [ 0.199941] CPU7: Booted secondary processor [ 0.199944] Detected VIPT I-cache on CPU7 [ 0.200014] Brought up 8 CPUs [ 0.200049] SMP: Total of 8 processors activated. [ 0.200626] devtmpfs: initialized [ 0.204994] xor: measuring software checksum speed [ 0.299605] 8regs : 2381.600 MB/sec [ 0.399639] 8regs_prefetch: 2176.000 MB/sec [ 0.499674] 32regs : 2639.200 MB/sec [ 0.599708] 32regs_prefetch: 2321.600 MB/sec [ 0.599714] xor: using function: 32regs (2639.200 MB/sec) <snip>

9 years, 2 months

Issue booting Hikey from SD card

by Lee Jones

After following the instructions in the Quick Start Guide for booting from SD card I receive: [tux.img][tux.img][tux.img][tux.img][tux.img][tux.img][tux.img][tux.img] [STAMP] kvm [1]: HYP mode not available [STAMP] of_dma_request_slave_channel: dma-names property of node '/smb/uart@f8015000' missing or empty [STAMP] hisi_thermal f7030700.tsensor: THERMAL ALARM: T > 80 <DEAD> Has anyone else seen this? Is it a known issue, or all-my-fault(tm)? NB: This is 'hikey-jessie_alip_20150701-323.img'. Booting 'hikey-jessie_developer_20150701-323.emmc.img' from eMMC works fine. Kind regards, Lee -- Lee Jones Linaro ST Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog

9 years, 2 months

[ANN] Linaro Linux/Ubuntu 15.09 release for DragonBoard 410c is available

by Nicolas Dechesne

hello there, A new release Linux release for the DragonBoard 410c is now available. The Linaro Linux release 15.09 is an Ubuntu-based Linaro Build that provides developers with a desktop like environment using Ubuntu and the LXDE desktop, as well as a console-only image. What’s new in 15.09 release? * Based on Linux kernel v4.2 * Support for Grove Starter Kit for 96boards * Initial support for high speed UART (with DMA) * Initial support for X11/GLAMOR * Various bug fixes reported on Bugzilla. For more details and the list of bug fixes, or to download the release, please go to: http://builds.96boards.org/releases/dragonboard410c/linaro/ubuntu/15.09 For general question or support request, please go to 96boards Community forum: https://www.96boards.org/dragonboard410c/forum For any bug related to this release, please submit issues to the 96Boards Bug tracking system: https://bugs.96boards.org/enter_bug.cgi?product=Dragonboard%20410c Finally, to get in touch with us, you can also use IRC: #96boards on irc.freenode.net Note that we will be moving to Debian (stable) instead of Ubuntu shortly for the the DragonBoard 410c Linux releases. We do not anticipate any feature changes, and for most users that should be transparent. Debian is used for all other 96boards , so we are making this change to align with the rest of 96boards. On behalf of the Linaro Qualcomm Landing team, cheers, Nicolas

9 years, 2 months

Re: [Dev] Draft 96Boards Sensors Kit Getting Started Guide

by Grant Likely

[cc'ing dev list. This can be discussed in public] On Wed, Sep 30, 2015 at 12:37 PM, Daniel Thompson <daniel.thompson(a)linaro.org> wrote: > Hi Grant > > On 28/09/15 15:57, Grant Likely wrote: >> >> On Mon, Sep 28, 2015 at 3:47 PM, Grant Likely <grant.likely(a)linaro.org> >> wrote: >>> >>> Update on the Sensors board. >>> >>> Unfortunately, some of the boards got shipped out without the Arduino >>> bootloader installed on the Atmel. Before you can use the procedure in >>> the starter guide, you'll need to disconnect the Sensors board from >>> your 96boards baseboard and flash the bootloader. Pretty much any >>> flashing method will work, but the easiest is probably to use another >>> Arduino as a programmer as documented here (unless you already have an >>> AVR-ISP programmer, in which case use that): >>> >>> https://www.arduino.cc/en/Tutorial/ArduinoISP >>> >>> I've also updated the getting started guide. >>> >>> Sorry for the inconvenience. Let me know if you have any trouble >>> flashing the bootloader. >> >> >> Also, can you please let me know if your board was missing the >> bootloader, and if you were able to get it reflashed? > > > Not sure if you want private e-mail to report troubles with the AVR or if I > should put it on dev@... For now I've just done a straight reply but I'm > happy to widen things. > > > Either but anyhow my sensors board really isn't doing what I would expect. > > I've run a quite a few different experiments after looking at the schematic > to try and figure out what is going on. The (somewhat lengthy) results are > as follows: > > 1. When power is applied to baseboard (Dragonboard 410c in my case) the > PB5 LED (red) comes on briefly then goes out and it replaced by the > reset LED (blue). > > 2. avrdude (run via make upload) fails with "avrdude: stk500_getsync() > attempt 1 of 10: not in sync: resp=0x00" errors. When avrdude is run > the blue LED goes out and PB5 starts to blink. Sounds like the bootloader is indeed missing and the manufacturing test sketch is still on the board. The test sketch blinks LEDs on all the pins. > 3. Running avrdude again interrupts the timing of the blink sequence > It looks like avrdude can place the AVR into reset.reset. Yes, that sounds right. > 4. Shorting UART0 TX/RX on the LS connector (with the sensors board > not fitted) results in character echo so we know the Dragonboard UART > is able to send receive characters. > > 5. Shorting TX/RX after level shifting does *not* result in character > echo. I tried on the arduino connector (P5) and directly on AVR pins > 30 and 31. This may not work as the AVR is also driving the UART RX signal. It probably prevents the signal from going low enough to be detected. > 6. I can light D7 using GPIO36 and the sysfs interface although the > lamp strength is very weak. I will check into that on my board. > 7. Connecting a SW to P12 allows me to read the state of the switch. > D7 also lights up and the lamp strength is much brighter. This is > since in both cases > > 8. USBtinyISP cannot program the AVR using the ISP connector. I have > checked the programmer with another ATMega328P based board and it is > working OK. I've not tried the ISP connector. It may be that we screwed it up somehow. George, have you tried it? This was the very first batch of boards, so there are things that I know are wrong and will be fixed before going into production. > ~~~ > ... > avrdude: Using SCK period of 10 usec > avrdude: initialization failed, rc=-1 > Double check connections and try again, or use -F to override > this check. > ~~~ > > 9. (I suspect you have already discovered this but just in case...) the > P2 (arduino 1x10) and P3 (ISP) are too close together to allow > a normal IDC connector to be attached to P3. ;-) For the next run I want to move the ISP connector down to the same location it is on a real arduino. That will solve the connector problem and also make it compatible with more shields. > I'm pretty confused at this point, to the point of suspecting multiple > faults. Next steps for me will be with a continuity tester... Actually, most of this sounds to be symptoms of a missing bootloader. Since you can't get USBtinyISP to program the board, do you have an arduino board handy that you can run the ArduinoISP sketch on? I used the following instructions for flashing the bootloader: https://www.arduino.cc/en/Tutorial/ArduinoISP Feel free to make comments on the Getting Started guide as you find things. https://docs.google.com/document/d/1GNoC-1C1xcejgLLvgm1JbpF7blwJigXq5XIB3Fv… g.

9 years, 2 months

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Dev October 2015