The patch series also have been send pull request at git-hub: https://github.com/96boards/arm-trusted-firmware/pull/6 Also send to mailing list to get more feedback and review.
On hi6220, the mcu firmware image will be loaded so that later kernel can use cpufreq successfully. So below patches are trying to enable this feature.
During the debugging, found it's very fragile for the registers' order, so add memory barrier for mmio register accessing; this is fixed by patch 1;
The mcu image loading are mainly finished by patch 3/6; But the mcu will not work well until init the paramters within sram and enable some clocks before enable mcu, so other dvfs/hkadc related patches are trying to enable this part.
Leo Yan (11): Add memory barrier for mmio accessing hikey: re-work for register files hikey: add mcu image loading driver hikey: add hkadc driver support hikey: add header file for sram hikey: load mcu binary in BL2 Load BL30 after io storage has been initialized hikey: BL1: polish register definition hikey: add support for dvfs driver hikey: add building for adc/mcu/acpu drivers hikey: support dvfs in pll main flow
bl2/bl2_main.c | 6 +- include/lib/mmio.h | 22 +- plat/hikey/aarch64/hikey_common.c | 6 + plat/hikey/bl1_plat_setup.c | 10 +- plat/hikey/bl2_plat_setup.c | 40 ++ plat/hikey/drivers/hisi_adc.c | 218 +++++++++ plat/hikey/drivers/hisi_dvfs.c | 775 ++++++++++++++++++++++++++++++++ plat/hikey/drivers/hisi_mcu.c | 247 ++++++++++ plat/hikey/hikey_def.h | 3 + plat/hikey/include/hi6220.h | 308 +------------ plat/hikey/include/hi6220_regs_acpu.h | 321 +++++++++++++ plat/hikey/include/hi6220_regs_ao.h | 357 +++++++++++++++ plat/hikey/include/hi6220_regs_peri.h | 404 +++++++++++++++++ plat/hikey/include/hi6220_regs_pmctrl.h | 126 ++++++ plat/hikey/include/hi6553.h | 4 + plat/hikey/include/hisi_hkadc.h | 152 +++++++ plat/hikey/include/hisi_mcu.h | 41 ++ plat/hikey/include/hisi_sram_map.h | 307 +++++++++++++ plat/hikey/include/platform_def.h | 8 +- plat/hikey/plat_io_storage.c | 10 + plat/hikey/platform.mk | 3 + plat/hikey/pll.c | 15 +- plat/hikey/usb.c | 22 +- 23 files changed, 3079 insertions(+), 326 deletions(-) create mode 100644 plat/hikey/drivers/hisi_adc.c create mode 100644 plat/hikey/drivers/hisi_dvfs.c create mode 100644 plat/hikey/drivers/hisi_mcu.c create mode 100644 plat/hikey/include/hi6220_regs_acpu.h create mode 100644 plat/hikey/include/hi6220_regs_ao.h create mode 100644 plat/hikey/include/hi6220_regs_peri.h create mode 100644 plat/hikey/include/hi6220_regs_pmctrl.h create mode 100644 plat/hikey/include/hisi_hkadc.h create mode 100644 plat/hikey/include/hisi_mcu.h create mode 100644 plat/hikey/include/hisi_sram_map.h
Add memory barrier for mmio write and read operations, so that it will be much stable for initialization.
Signed-off-by: Leo Yan leo.yan@linaro.org --- include/lib/mmio.h | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/include/lib/mmio.h b/include/lib/mmio.h index cb37a1c..e43cd93 100644 --- a/include/lib/mmio.h +++ b/include/lib/mmio.h @@ -31,36 +31,52 @@ #ifndef __MMIO_H__ #define __MMIO_H__
+#include <arch_helpers.h> #include <stdint.h>
static inline void mmio_write_8(uintptr_t addr, uint8_t value) { + dsb(); *(volatile uint8_t*)addr = value; }
static inline uint8_t mmio_read_8(uintptr_t addr) { - return *(volatile uint8_t*)addr; + uint8_t val; + + val = *(volatile uint8_t*)addr; + dsb(); + return val; }
static inline void mmio_write_32(uintptr_t addr, uint32_t value) { + dsb(); *(volatile uint32_t*)addr = value; }
static inline uint32_t mmio_read_32(uintptr_t addr) { - return *(volatile uint32_t*)addr; + uint32_t val; + + val = *(volatile uint32_t*)addr; + dsb(); + return val; }
static inline void mmio_write_64(uintptr_t addr, uint64_t value) { + dsb(); *(volatile uint64_t*)addr = value; }
static inline uint64_t mmio_read_64(uintptr_t addr) { - return *(volatile uint64_t*)addr; + uint64_t val; + + val = *(volatile uint64_t*)addr; + dsb(); + return val; }
#endif /* __MMIO_H__ */
On Tue, Mar 24, 2015 at 10:25 PM, Leo Yan leo.yan@linaro.org wrote:
Add memory barrier for mmio write and read operations, so that it will be much stable for initialization.
Are you sure you don't have the MMU mapping incorrect? These should not be needed with proper mappings.
Looking at the other patches, I would guess you have some ordering problem between SRAM writes and register writes. I'm just guessing as I have no clue what exactly is not stable. You should put barriers where needed rather than wholesale barrier in every register access.
Rob
Signed-off-by: Leo Yan leo.yan@linaro.org
include/lib/mmio.h | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/include/lib/mmio.h b/include/lib/mmio.h index cb37a1c..e43cd93 100644 --- a/include/lib/mmio.h +++ b/include/lib/mmio.h @@ -31,36 +31,52 @@ #ifndef __MMIO_H__ #define __MMIO_H__
+#include <arch_helpers.h> #include <stdint.h>
static inline void mmio_write_8(uintptr_t addr, uint8_t value) {
dsb(); *(volatile uint8_t*)addr = value;}
static inline uint8_t mmio_read_8(uintptr_t addr) {
return *(volatile uint8_t*)addr;
uint8_t val;val = *(volatile uint8_t*)addr;dsb();return val;}
static inline void mmio_write_32(uintptr_t addr, uint32_t value) {
dsb(); *(volatile uint32_t*)addr = value;}
static inline uint32_t mmio_read_32(uintptr_t addr) {
return *(volatile uint32_t*)addr;
uint32_t val;val = *(volatile uint32_t*)addr;dsb();return val;}
static inline void mmio_write_64(uintptr_t addr, uint64_t value) {
dsb(); *(volatile uint64_t*)addr = value;}
static inline uint64_t mmio_read_64(uintptr_t addr) {
return *(volatile uint64_t*)addr;
uint64_t val;val = *(volatile uint64_t*)addr;dsb();return val;}
#endif /* __MMIO_H__ */
1.9.1
Dev mailing list Dev@lists.96boards.org https://lists.96boards.org/mailman/listinfo/dev
On Tue, Mar 24, 2015 at 10:45:41PM -0500, Rob Herring wrote:
On Tue, Mar 24, 2015 at 10:25 PM, Leo Yan leo.yan@linaro.org wrote:
Add memory barrier for mmio write and read operations, so that it will be much stable for initialization.
Are you sure you don't have the MMU mapping incorrect? These should not be needed with proper mappings.
All register regions are mapped as device type: Device-nGnRE; This mapping type is weaker than strong order.
In the code, there have many registers accessing need set different controller's registers to finish one operation; if there have several outstanding transaction to different endpoints, then if we don't add the DSB() b/t them, it's easily introduce the timing issue.
Looking at the other patches, I would guess you have some ordering problem between SRAM writes and register writes. I'm just guessing as I have no clue what exactly is not stable. You should put barriers where needed rather than wholesale barrier in every register access.
This issue has been reported before. So i committed one patch to add dsb()/isb() after pll's initialization, but it's still fragile when i do the testing w/t system reset.
Actually i have tried add more barriers into init flow, but it's no luck until i apply this patch; that also stands i'm not familiar w/t this SoC. :)
Anyway, i will try to review the init flow again and add more barriers as i can.
Rob
Signed-off-by: Leo Yan leo.yan@linaro.org
include/lib/mmio.h | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/include/lib/mmio.h b/include/lib/mmio.h index cb37a1c..e43cd93 100644 --- a/include/lib/mmio.h +++ b/include/lib/mmio.h @@ -31,36 +31,52 @@ #ifndef __MMIO_H__ #define __MMIO_H__
+#include <arch_helpers.h> #include <stdint.h>
static inline void mmio_write_8(uintptr_t addr, uint8_t value) {
dsb(); *(volatile uint8_t*)addr = value;}
static inline uint8_t mmio_read_8(uintptr_t addr) {
return *(volatile uint8_t*)addr;
uint8_t val;val = *(volatile uint8_t*)addr;dsb();return val;}
static inline void mmio_write_32(uintptr_t addr, uint32_t value) {
dsb(); *(volatile uint32_t*)addr = value;}
static inline uint32_t mmio_read_32(uintptr_t addr) {
return *(volatile uint32_t*)addr;
uint32_t val;val = *(volatile uint32_t*)addr;dsb();return val;}
static inline void mmio_write_64(uintptr_t addr, uint64_t value) {
dsb(); *(volatile uint64_t*)addr = value;}
static inline uint64_t mmio_read_64(uintptr_t addr) {
return *(volatile uint64_t*)addr;
uint64_t val;val = *(volatile uint64_t*)addr;dsb();return val;}
#endif /* __MMIO_H__ */
1.9.1
Dev mailing list Dev@lists.96boards.org https://lists.96boards.org/mailman/listinfo/dev
There have several kinds for registers, which have many registers and definition for them. So use the dedicated header file for acpu/ao/peripheral/power controller, so that can easily extend the definition for registers.
Signed-off-by: Leo Yan leo.yan@linaro.org --- plat/hikey/include/hi6220.h | 308 +----------------------- plat/hikey/include/hi6220_regs_acpu.h | 321 +++++++++++++++++++++++++ plat/hikey/include/hi6220_regs_ao.h | 357 ++++++++++++++++++++++++++++ plat/hikey/include/hi6220_regs_peri.h | 404 ++++++++++++++++++++++++++++++++ plat/hikey/include/hi6220_regs_pmctrl.h | 126 ++++++++++ plat/hikey/include/hi6553.h | 4 + plat/hikey/usb.c | 22 +- 7 files changed, 1234 insertions(+), 308 deletions(-) create mode 100644 plat/hikey/include/hi6220_regs_acpu.h create mode 100644 plat/hikey/include/hi6220_regs_ao.h create mode 100644 plat/hikey/include/hi6220_regs_peri.h create mode 100644 plat/hikey/include/hi6220_regs_pmctrl.h
diff --git a/plat/hikey/include/hi6220.h b/plat/hikey/include/hi6220.h index a49e320..e9d80ee 100644 --- a/plat/hikey/include/hi6220.h +++ b/plat/hikey/include/hi6220.h @@ -32,310 +32,22 @@ #ifndef __HI6220_H__ #define __HI6220_H__
+#include <hi6220_regs_acpu.h> +#include <hi6220_regs_ao.h> +#include <hi6220_regs_peri.h> +#include <hi6220_regs_pmctrl.h> + +#include <hisi_hkadc.h> +#include <hisi_mcu.h> +#include <hisi_sram_map.h> + #define MEDIA_CTRL_BASE 0xf4410000 #define MEDIA_SUBSYS_CTRL2 (MEDIA_CTRL_BASE + 0x508) #define MEDIA_SUBSYS_NOC_DFS (MEDIA_CTRL_BASE + 0x510) #define MEDIA_SUBSYS_CTRL5 (MEDIA_CTRL_BASE + 0x51c)
-#define ACPU_CTRL_BASE 0xf6504000 -#define ACPU_SC_CPU_CTRL (ACPU_CTRL_BASE + 0x000) -#define ACPU_SC_CPU_STAT (ACPU_CTRL_BASE + 0x008) -#define ACPU_SC_CLKEN (ACPU_CTRL_BASE + 0x00c) -#define HPM_L2_1_CLKEN (1 << 9) -#define G_CPU_1_CLKEN (1 << 8) -#define HPM_L2_CLKEN (1 << 1) -#define G_CPU_CLKEN (1 << 0) - -#define ACPU_SC_CLKDIS (ACPU_CTRL_BASE + 0x010) -#define ACPU_SC_CLK_STAT (ACPU_CTRL_BASE + 0x014) -#define ACPU_SC_RSTEN (ACPU_CTRL_BASE + 0x018) -#define SRST_PRESET1_RSTEN (1 << 11) -#define SRST_PRESET0_RSTEN (1 << 10) -#define SRST_CLUSTER1_RSTEN (1 << 9) -#define SRST_CLUSTER0_RSTEN (1 << 8) -#define SRST_L2_HPM_1_RSTEN (1 << 5) -#define SRST_AARM_L2_1_RSTEN (1 << 4) -#define SRST_L2_HPM_0_RSTEN (1 << 3) -#define SRST_AARM_L2_0_RSTEN (1 << 1) -#define SRST_CLUSTER1 (SRST_PRESET1_RSTEN | \ - SRST_CLUSTER1_RSTEN | \ - SRST_L2_HPM_1_RSTEN | \ - SRST_AARM_L2_1_RSTEN) -#define SRST_CLUSTER0 (SRST_PRESET0_RSTEN | \ - SRST_CLUSTER0_RSTEN | \ - SRST_L2_HPM_0_RSTEN | \ - SRST_AARM_L2_0_RSTEN) - -#define ACPU_SC_RSTDIS (ACPU_CTRL_BASE + 0x01c) -#define ACPU_SC_RST_STAT (ACPU_CTRL_BASE + 0x020) -#define ACPU_SC_PDBGUP_MBIST (ACPU_CTRL_BASE + 0x02c) -#define PDBGUP_CLUSTER1_SHIFT 8 - -#define ACPU_SC_VD_CTRL (ACPU_CTRL_BASE + 0x054) -#define ACPU_SC_VD_MASK_PATTERN_CTRL (ACPU_CTRL_BASE + 0x058) -#define ACPU_SC_VD_DLY_FIXED_CTRL (ACPU_CTRL_BASE + 0x05c) -#define ACPU_SC_VD_DLY_TABLE0_CTRL (ACPU_CTRL_BASE + 0x060) -#define ACPU_SC_VD_DLY_TABLE1_CTRL (ACPU_CTRL_BASE + 0x064) -#define ACPU_SC_VD_DLY_TABLE2_CTRL (ACPU_CTRL_BASE + 0x068) -#define ACPU_SC_VD_HPM_CTRL (ACPU_CTRL_BASE + 0x06c) -#define ACPU_SC_A53_CLUSTER_MTCMOS_EN (ACPU_CTRL_BASE + 0x088) -#define PW_MTCMOS_EN_A53_1_EN (1 << 1) -#define PW_MTCMOS_EN_A53_0_EN (1 << 0) - -#define ACPU_SC_A53_CLUSTER_MTCMOS_STA (ACPU_CTRL_BASE + 0x090) -#define ACPU_SC_A53_CLUSTER_ISO_EN (ACPU_CTRL_BASE + 0x098) -#define PW_ISO_A53_1_EN (1 << 1) -#define PW_ISO_A53_0_EN (1 << 0) - -#define ACPU_SC_A53_CLUSTER_ISO_DIS (ACPU_CTRL_BASE + 0x09c) -#define ACPU_SC_A53_CLUSTER_ISO_STA (ACPU_CTRL_BASE + 0x0a0) -#define ACPU_SC_A53_1_MTCMOS_TIMER (ACPU_CTRL_BASE + 0x0b4) -#define ACPU_SC_A53_0_MTCMOS_TIMER (ACPU_CTRL_BASE + 0x0bc) -#define ACPU_SC_A53_x_MTCMOS_TIMER(x) ((x) ? ACPU_SC_A53_1_MTCMOS_TIMER : ACPU_SC_A53_0_MTCMOS_TIMER) - -#define ACPU_SC_CPU0_CTRL (ACPU_CTRL_BASE + 0x100) -#define CPU_CTRL_AARCH64_MODE (1 << 7) - -#define ACPU_SC_CPU0_STAT (ACPU_CTRL_BASE + 0x104) -#define ACPU_SC_CPU0_CLKEN (ACPU_CTRL_BASE + 0x108) -#define CPU_CLKEN_HPM (1 << 1) - -#define ACPU_SC_CPU0_CLK_STAT (ACPU_CTRL_BASE + 0x110) - -#define ACPU_SC_CPU0_RSTEN (ACPU_CTRL_BASE + 0x114) -#define ACPU_SC_CPU0_RSTDIS (ACPU_CTRL_BASE + 0x118) -#define ACPU_SC_CPU0_MTCMOS_EN (ACPU_CTRL_BASE + 0x120) -#define CPU_MTCMOS_PW (1 << 0) - -#define ACPU_SC_CPU0_PW_ISOEN (ACPU_CTRL_BASE + 0x130) -#define CPU_PW_ISO (1 << 0) - -#define ACPU_SC_CPU0_PW_ISODIS (ACPU_CTRL_BASE + 0x134) -#define ACPU_SC_CPU0_PW_ISO_STAT (ACPU_CTRL_BASE + 0x138) -#define ACPU_SC_CPU0_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x154) -#define CPU_MTCMOS_TIMER_STA (1 << 0) - -#define ACPU_SC_CPU0_RVBARADDR (ACPU_CTRL_BASE + 0x158) -#define ACPU_SC_CPU1_CTRL (ACPU_CTRL_BASE + 0x200) -#define ACPU_SC_CPU1_STAT (ACPU_CTRL_BASE + 0x204) -#define ACPU_SC_CPU1_CLKEN (ACPU_CTRL_BASE + 0x208) -#define ACPU_SC_CPU1_CLK_STAT (ACPU_CTRL_BASE + 0x210) -#define ACPU_SC_CPU1_RSTEN (ACPU_CTRL_BASE + 0x214) -#define ACPU_SC_CPU1_RSTDIS (ACPU_CTRL_BASE + 0x218) -#define ACPU_SC_CPU1_MTCMOS_EN (ACPU_CTRL_BASE + 0x220) -#define ACPU_SC_CPU1_PW_ISODIS (ACPU_CTRL_BASE + 0x234) -#define ACPU_SC_CPU1_PW_ISO_STAT (ACPU_CTRL_BASE + 0x238) -#define ACPU_SC_CPU1_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x254) -#define ACPU_SC_CPU1_RVBARADDR (ACPU_CTRL_BASE + 0x258) -#define ACPU_SC_CPU2_CTRL (ACPU_CTRL_BASE + 0x300) -#define ACPU_SC_CPU2_STAT (ACPU_CTRL_BASE + 0x304) -#define ACPU_SC_CPU2_CLKEN (ACPU_CTRL_BASE + 0x308) -#define ACPU_SC_CPU2_CLK_STAT (ACPU_CTRL_BASE + 0x310) -#define ACPU_SC_CPU2_RSTEN (ACPU_CTRL_BASE + 0x314) -#define ACPU_SC_CPU2_RSTDIS (ACPU_CTRL_BASE + 0x318) -#define ACPU_SC_CPU2_MTCMOS_EN (ACPU_CTRL_BASE + 0x320) -#define ACPU_SC_CPU2_PW_ISODIS (ACPU_CTRL_BASE + 0x334) -#define ACPU_SC_CPU2_PW_ISO_STAT (ACPU_CTRL_BASE + 0x338) -#define ACPU_SC_CPU2_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x354) -#define ACPU_SC_CPU2_RVBARADDR (ACPU_CTRL_BASE + 0x358) -#define ACPU_SC_CPU3_CTRL (ACPU_CTRL_BASE + 0x400) -#define ACPU_SC_CPU3_STAT (ACPU_CTRL_BASE + 0x404) -#define ACPU_SC_CPU3_CLKEN (ACPU_CTRL_BASE + 0x408) -#define ACPU_SC_CPU3_CLK_STAT (ACPU_CTRL_BASE + 0x410) -#define ACPU_SC_CPU3_RSTEN (ACPU_CTRL_BASE + 0x414) -#define ACPU_SC_CPU3_RSTDIS (ACPU_CTRL_BASE + 0x418) -#define ACPU_SC_CPU3_MTCMOS_EN (ACPU_CTRL_BASE + 0x420) -#define ACPU_SC_CPU3_PW_ISODIS (ACPU_CTRL_BASE + 0x434) -#define ACPU_SC_CPU3_PW_ISO_STAT (ACPU_CTRL_BASE + 0x438) -#define ACPU_SC_CPU3_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x454) -#define ACPU_SC_CPU3_RVBARADDR (ACPU_CTRL_BASE + 0x458) -#define ACPU_SC_CPU4_CTRL (ACPU_CTRL_BASE + 0x500) -#define ACPU_SC_CPU4_STAT (ACPU_CTRL_BASE + 0x504) -#define ACPU_SC_CPU4_CLKEN (ACPU_CTRL_BASE + 0x508) -#define ACPU_SC_CPU4_CLK_STAT (ACPU_CTRL_BASE + 0x510) -#define ACPU_SC_CPU4_RSTEN (ACPU_CTRL_BASE + 0x514) -#define ACPU_SC_CPU4_RSTDIS (ACPU_CTRL_BASE + 0x518) -#define ACPU_SC_CPU4_MTCMOS_EN (ACPU_CTRL_BASE + 0x520) -#define ACPU_SC_CPU4_PW_ISODIS (ACPU_CTRL_BASE + 0x534) -#define ACPU_SC_CPU4_PW_ISO_STAT (ACPU_CTRL_BASE + 0x538) -#define ACPU_SC_CPU4_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x554) -#define ACPU_SC_CPU4_RVBARADDR (ACPU_CTRL_BASE + 0x558) -#define ACPU_SC_CPU5_CTRL (ACPU_CTRL_BASE + 0x600) -#define ACPU_SC_CPU5_STAT (ACPU_CTRL_BASE + 0x604) -#define ACPU_SC_CPU5_CLKEN (ACPU_CTRL_BASE + 0x608) -#define ACPU_SC_CPU5_CLK_STAT (ACPU_CTRL_BASE + 0x610) -#define ACPU_SC_CPU5_RSTEN (ACPU_CTRL_BASE + 0x614) -#define ACPU_SC_CPU5_RSTDIS (ACPU_CTRL_BASE + 0x618) -#define ACPU_SC_CPU5_MTCMOS_EN (ACPU_CTRL_BASE + 0x620) -#define ACPU_SC_CPU5_PW_ISODIS (ACPU_CTRL_BASE + 0x634) -#define ACPU_SC_CPU5_PW_ISO_STAT (ACPU_CTRL_BASE + 0x638) -#define ACPU_SC_CPU5_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x654) -#define ACPU_SC_CPU5_RVBARADDR (ACPU_CTRL_BASE + 0x658) -#define ACPU_SC_CPU6_CTRL (ACPU_CTRL_BASE + 0x700) -#define ACPU_SC_CPU6_STAT (ACPU_CTRL_BASE + 0x704) -#define ACPU_SC_CPU6_CLKEN (ACPU_CTRL_BASE + 0x708) -#define ACPU_SC_CPU6_CLK_STAT (ACPU_CTRL_BASE + 0x710) -#define ACPU_SC_CPU6_RSTEN (ACPU_CTRL_BASE + 0x714) -#define ACPU_SC_CPU6_RSTDIS (ACPU_CTRL_BASE + 0x718) -#define ACPU_SC_CPU6_MTCMOS_EN (ACPU_CTRL_BASE + 0x720) -#define ACPU_SC_CPU6_PW_ISODIS (ACPU_CTRL_BASE + 0x734) -#define ACPU_SC_CPU6_PW_ISO_STAT (ACPU_CTRL_BASE + 0x738) -#define ACPU_SC_CPU6_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x754) -#define ACPU_SC_CPU6_RVBARADDR (ACPU_CTRL_BASE + 0x758) -#define ACPU_SC_CPU7_CTRL (ACPU_CTRL_BASE + 0x800) -#define ACPU_SC_CPU7_STAT (ACPU_CTRL_BASE + 0x804) -#define ACPU_SC_CPU7_CLKEN (ACPU_CTRL_BASE + 0x808) -#define ACPU_SC_CPU7_CLK_STAT (ACPU_CTRL_BASE + 0x810) -#define ACPU_SC_CPU7_RSTEN (ACPU_CTRL_BASE + 0x814) -#define ACPU_SC_CPU7_RSTDIS (ACPU_CTRL_BASE + 0x818) -#define ACPU_SC_CPU7_MTCMOS_EN (ACPU_CTRL_BASE + 0x820) -#define ACPU_SC_CPU7_PW_ISODIS (ACPU_CTRL_BASE + 0x834) -#define ACPU_SC_CPU7_PW_ISO_STAT (ACPU_CTRL_BASE + 0x838) -#define ACPU_SC_CPU7_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x854) -#define ACPU_SC_CPU7_RVBARADDR (ACPU_CTRL_BASE + 0x858) -#define ACPU_SC_CPUx_CTRL(x) ((x < 8) ? (ACPU_SC_CPU0_CTRL + 0x100 * x) : ACPU_SC_CPU0_CTRL) -#define ACPU_SC_CPUx_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_STAT + 0x100 * x) : ACPU_SC_CPU0_STAT) -#define ACPU_SC_CPUx_CLKEN(x) ((x < 8) ? (ACPU_SC_CPU0_CLKEN + 0x100 * x) : ACPU_SC_CPU0_CLKEN) -#define ACPU_SC_CPUx_CLK_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_CLK_STAT + 0x100 *x) : ACPU_SC_CPU0_CLK_STAT) -#define ACPU_SC_CPUx_RSTEN(x) ((x < 8) ? (ACPU_SC_CPU0_RSTEN + 0x100 * x) : ACPU_SC_CPU0_RSTEN) -#define ACPU_SC_CPUx_RSTDIS(x) ((x < 8) ? (ACPU_SC_CPU0_RSTDIS + 0x100 * x) : ACPU_SC_CPU0_RSTDIS) -#define ACPU_SC_CPUx_MTCMOS_EN(x) ((x < 8) ? (ACPU_SC_CPU0_MTCMOS_EN + 0x100 * x) : ACPU_SC_CPU0_MTCMOS_EN) -#define ACPU_SC_CPUx_PW_ISODIS(x) ((x < 8) ? (ACPU_SC_CPU0_PW_ISODIS + 0x100 * x) : ACPU_SC_CPU0_PW_ISODIS) -#define ACPU_SC_CPUx_PW_ISO_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_PW_ISO_STAT + 0x100 * x) : ACPU_SC_CPU0_PW_ISO_STAT) -#define ACPU_SC_CPUx_MTCMOS_TIMER_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_MTCMOS_TIMER_STAT + 0x100 * x) : ACPU_SC_CPU0_MTCMOS_TIMER_STAT) -#define ACPU_SC_CPUx_RVBARADDR(x) ((x < 8) ? (ACPU_SC_CPU0_RVBARADDR + 0x100 * x) : ACPU_SC_CPU0_RVBARADDR) - -#define ACPU_SC_CPU_STAT_CLKDIV_VD_MASK (3 << 20) - -#define ACPU_SC_VD_CTRL_TUNE_EN_DIF (1 << 0) -#define ACPU_SC_VD_CTRL_TUNE_EN_INT (1 << 11) -#define ACPU_SC_VD_CTRL_SHIFT_TABLE0_MASK (0xf << 12) -#define ACPU_SC_VD_CTRL_FORCE_CLK_EN (1 << 28) - -#define ACPU_SC_VD_MASK_PATTERN ((1 << 13) - 1) - -#define ACPU_SC_VD_HPM_CTRL_OSC_DIV_MASK 0xffff -#define ACPU_SC_VD_HPM_CTRL_DLY_EXP_MASK (0xffffff << 8) - -#define PERI_BASE 0xf7030000 -#define PERI_SC_PERIPH_CTRL2 (PERI_BASE + 0x004) -#define PERI_SC_PERIPH_CTRL4 (PERI_BASE + 0x00c) -#define PERI_SC_PERIPH_CTRL5 (PERI_BASE + 0x010) -#define PERI_SC_PERIPH_CTRL8 (PERI_BASE + 0x018) -#define PERI_SC_PERIPH_CTRL13 (PERI_BASE + 0x028) -#define PERI_SC_PERIPH_CTRL14 (PERI_BASE + 0x02c) -#define PERI_SC_DDR_CTRL0 (PERI_BASE + 0x050) -#define PERI_SC_PERIPH_STAT1 (PERI_BASE + 0x094) -#define PERI_SC_PERIPH_CLKEN0 (PERI_BASE + 0x200) -#define PERI_SC_PERIPH_CLKDIS0 (PERI_BASE + 0x204) -#define PERI_SC_PERIPH_CLKSTAT0 (PERI_BASE + 0x208) -#define PERI_SC_PERIPH_CLKEN8 (PERI_BASE + 0x240) -#define PERI_SC_PERIPH_CLKEN12 (PERI_BASE + 0x270) -#define PERI_SC_PERIPH_RSTEN0 (PERI_BASE + 0x300) -#define PERI_SC_PERIPH_RSTDIS0 (PERI_BASE + 0x304) -#define PERI_SC_PERIPH_RSTSTAT0 (PERI_BASE + 0x308) -#define PERI_SC_PERIPH_RSTEN8 (PERI_BASE + 0x340) -#define PERI_SC_PERIPH_RSTDIS8 (PERI_BASE + 0x344) -#define PERI_SC_CLK_SEL0 (PERI_BASE + 0x400) -#define PERI_SC_CLKCFG8BIT1 (PERI_BASE + 0x494) - -#define PCLK_TIMER1 (1 << 16) -#define PCLK_TIMER0 (1 << 15) - -#define PERIPH_CTRL4_OTG_PHY_SEL (1 << 21) -#define PERIPH_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11) -#define PERIPH_CTRL4_PICO_VBUSVLDEXT (1 << 10) -#define PERIPH_CTRL4_PICO_SIDDQ (1 << 6) -#define PERIPH_CTRL4_FPGA_EXT_PHY_SEL (1 << 3) - -#define PERIPH_CTRL5_PICOPHY_BC_MODE (1 << 5) - -#define PERIPH_CTRL14_FM_CLK_SEL_SHIFT 8 -#define PERIPH_CTRL14_FM_EN (1 << 0) - -#define PERI_CLK_USBOTG (1 << 4) -#define PERI_CLK_MMC2 (1 << 2) -#define PERI_CLK_MMC1 (1 << 1) -#define PERI_CLK_MMC0 (1 << 0) - -#define PERI_RST_USBOTG_32K (1 << 7) -#define PERI_RST_USBOTG (1 << 6) -#define PERI_RST_PICOPHY (1 << 5) -#define PERI_RST_USBOTG_BUS (1 << 4) -#define PERI_RST_MMC2 (1 << 2) -#define PERI_RST_MMC1 (1 << 1) -#define PERI_RST_MMC0 (1 << 0) - -#define PMCTRL_BASE 0xf7032000 -#define PMCTRL_ACPUPLLCTRL (PMCTRL_BASE + 0x000) -#define PMCTRL_ACPUPLLFREQ (PMCTRL_BASE + 0x004) -#define PMCTRL_DDRPLL1CTRL (PMCTRL_BASE + 0x010) -#define PMCTRL_DDRPLL0CTRL (PMCTRL_BASE + 0x030) -#define PMCTRL_MEDPLLCTRL (PMCTRL_BASE + 0x038) -#define PMCTRL_ACPUPLLSEL (PMCTRL_BASE + 0x100) -#define PMCTRL_ACPUCLKDIV (PMCTRL_BASE + 0x104) -#define PMCTRL_ACPUSYSPLLCFG (PMCTRL_BASE + 0x110) -#define PMCTRL_ACPUCLKOFFCFG (PMCTRL_BASE + 0x114) -#define PMCTRL_ACPUPLLFRAC (PMCTRL_BASE + 0x134) -#define PMCTRL_ACPUPMUVOLUPTIME (PMCTRL_BASE + 0x360) -#define PMCTRL_ACPUPMUVOLDNTIME (PMCTRL_BASE + 0x364) -#define PMCTRL_ACPUVOLPMUADDR (PMCTRL_BASE + 0x368) -#define PMCTRL_ACPUVOLUPSTEP (PMCTRL_BASE + 0x36c) -#define PMCTRL_ACPUVOLDNSTEP (PMCTRL_BASE + 0x370) -#define PMCTRL_ACPUDFTVOL (PMCTRL_BASE + 0x374) -#define PMCTRL_ACPUDESTVOL (PMCTRL_BASE + 0x378) -#define PMCTRL_ACPUVOLTTIMEOUT (PMCTRL_BASE + 0x37c) - -#define PMCTRL_ACPUPLLCTRL_EN_CFG (1 << 0) - -#define PMCTRL_ACPUCLKDIV_CPUEXT_CFG_MASK (3 << 0) -#define PMCTRL_ACPUCLKDIV_DDR_CFG_MASK (3 << 8) -#define PMCTRL_ACPUCLKDIV_CPUEXT_STAT_MASK (3 << 16) -#define PMCTRL_ACPUCLKDIV_DDR_STAT_MASK (3 << 24) - -#define PMCTRL_ACPUPLLSEL_ACPUPLL_CFG (1 << 0) -#define PMCTRL_ACPUPLLSEL_ACPUPLL_STAT (1 << 1) -#define PMCTRL_ACPUPLLSEL_SYSPLL_STAT (1 << 2) - -#define PMCTRL_ACPUSYSPLL_CLKDIV_CFG_MASK 0x7 -#define PMCTRL_ACPUSYSPLL_CLKEN_CFG (1 << 4) -#define PMCTRL_ACPUSYSPLL_CLKDIV_SW (3 << 12) - -#define PMCTRL_ACPUSYSPLLCFG_SYSPLL_CLKEN (1 << 4) -#define PMCTRL_ACPUSYSPLLCFG_CLKDIV_MASK (3 << 12) - -#define PMCTRL_ACPUDESTVOL_DEST_VOL_MASK 0x7f -#define PMCTRL_ACPUDESTVOL_CURR_VOL_MASK (0x7f << 8) - #define MMC0_BASE 0xf723d000
-#define AO_CTRL_BASE 0xf7800000 -#define AO_SC_SYS_CTRL0 (AO_CTRL_BASE + 0x000) -#define AO_SC_SYS_STAT0 (AO_CTRL_BASE + 0x010) -#define AO_SC_SYS_STAT1 (AO_CTRL_BASE + 0x014) -#define AO_SC_MCU_SUBSYS_CTRL3 (AO_CTRL_BASE + 0x40c) -#define AO_SC_PERIPH_CLKEN4 (AO_CTRL_BASE + 0x630) -#define AO_SC_PERIPH_CLKDIS4 (AO_CTRL_BASE + 0x634) -#define AO_SC_PERIPH_CLKSTAT4 (AO_CTRL_BASE + 0x638) -#define AO_SC_PERIPH_CLKEN5 (AO_CTRL_BASE + 0x63c) -#define AO_SC_PERIPH_RSTEN4 (AO_CTRL_BASE + 0x6f0) -#define AO_SC_PERIPH_RSTDIS4 (AO_CTRL_BASE + 0x6f4) -#define AO_SC_PERIPH_RSTSTAT4 (AO_CTRL_BASE + 0x6f8) -#define AO_SC_ECONUM (AO_CTRL_BASE + 0xf00) -#define AO_SC_TIMER_EN0 (AO_CTRL_BASE + 0x1d0) -#define AO_SC_TIMER_EN1 (AO_CTRL_BASE + 0x1d4) - -#define AO_SC_SYS_CTRL0_MODE_NORMAL 0x004 -#define AO_SC_SYS_CTRL0_MODE_MASK 0x007 - -#define AO_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003 -#define AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007 - -#define AO_SC_PERIPH_CLKEN4_PMUSSI (1 << 27) - -#define AO_SC_PERIPH_CLKEN5_PMUSSI_CCPU (1 << 0) -#define AO_SC_PERIPH_CLKEN5_PMUSSI_MCU (1 << 16) - #define PMUSSI_BASE 0xf8000000
#define TIMER0_BASE 0xf8008000 @@ -365,4 +77,6 @@ #define GPIO18_BASE 0xf702e000 #define GPIO19_BASE 0xf702f000
+extern void init_acpu_dvfs(void); + #endif /* __HI6220_H__ */ diff --git a/plat/hikey/include/hi6220_regs_acpu.h b/plat/hikey/include/hi6220_regs_acpu.h new file mode 100644 index 0000000..19dc15d --- /dev/null +++ b/plat/hikey/include/hi6220_regs_acpu.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. + * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __HI6220_REGS_ACPU_H__ +#define __HI6220_REGS_ACPU_H__ + +#define ACPU_CTRL_BASE 0xF6504000 + +#define ACPU_SC_CPU_CTRL (ACPU_CTRL_BASE + 0x000) +#define ACPU_SC_CPU_STAT (ACPU_CTRL_BASE + 0x008) +#define ACPU_SC_CPU_STAT_SC_STANDBYWFIL2 (1 << 0) +#define ACPU_SC_CPU_STAT_SC_STANDBYWFIL2_SHIFT (0) +#define ACPU_SC_CPU_STAT_SC_STANDBYWFI0 (1 << 1) +#define ACPU_SC_CPU_STAT_SC_STANDBYWFI0_SHIFT (1) +#define ACPU_SC_CPU_STAT_SC_STANDBYWFI1 (1 << 2) +#define ACPU_SC_CPU_STAT_SC_STANDBYWFI1_SHIFT (2) +#define ACPU_SC_CPU_STAT_SC_STANDBYWFI2 (1 << 3) +#define ACPU_SC_CPU_STAT_SC_STANDBYWFI2_SHIFT (3) +#define ACPU_SC_CPU_STAT_SC_STANDBYWFI3 (1 << 4) +#define ACPU_SC_CPU_STAT_SC_STANDBYWFI3_SHIFT (4) +#define ACPU_SC_CPU_STAT_A53_1_STANDBYWFIL2 (1 << 8) +#define ACPU_SC_CPU_STAT_A53_1_STANDBYWFIL2_SHIFT (8) +#define ACPU_SC_CPU_STAT_A53_1_STANDBYWFI (1 << 9) +#define ACPU_SC_CPU_STAT_A53_1_STANDBYWFI_SHIFT (9) +#define ACPU_SC_CPU_STAT_L2FLSHUDONE0 (1 << 16) +#define ACPU_SC_CPU_STAT_L2FLSHUDONE0_SHIFT (16) +#define ACPU_SC_CPU_STAT_L2FLSHUDONE1 (1 << 17) +#define ACPU_SC_CPU_STAT_L2FLSHUDONE1_SHIFT (17) +#define ACPU_SC_CPU_STAT_CCI400_ACTIVE (1 << 18) +#define ACPU_SC_CPU_STAT_CCI400_ACTIVE_SHIFT (18) +#define ACPU_SC_CPU_STAT_CLK_DIV_STATUS_VD (1 << 20) +#define ACPU_SC_CPU_STAT_CLK_DIV_STATUS_VD_SHIFT (20) + +#define ACPU_SC_CLKEN (ACPU_CTRL_BASE + 0x00c) +#define HPM_L2_1_CLKEN (1 << 9) +#define G_CPU_1_CLKEN (1 << 8) +#define HPM_L2_CLKEN (1 << 1) +#define G_CPU_CLKEN (1 << 0) + +#define ACPU_SC_CLKDIS (ACPU_CTRL_BASE + 0x010) +#define ACPU_SC_CLK_STAT (ACPU_CTRL_BASE + 0x014) +#define ACPU_SC_RSTEN (ACPU_CTRL_BASE + 0x018) +#define SRST_PRESET1_RSTEN (1 << 11) +#define SRST_PRESET0_RSTEN (1 << 10) +#define SRST_CLUSTER1_RSTEN (1 << 9) +#define SRST_CLUSTER0_RSTEN (1 << 8) +#define SRST_L2_HPM_1_RSTEN (1 << 5) +#define SRST_AARM_L2_1_RSTEN (1 << 4) +#define SRST_L2_HPM_0_RSTEN (1 << 3) +#define SRST_AARM_L2_0_RSTEN (1 << 1) +#define SRST_CLUSTER1 (SRST_PRESET1_RSTEN | \ + SRST_CLUSTER1_RSTEN | \ + SRST_L2_HPM_1_RSTEN | \ + SRST_AARM_L2_1_RSTEN) +#define SRST_CLUSTER0 (SRST_PRESET0_RSTEN | \ + SRST_CLUSTER0_RSTEN | \ + SRST_L2_HPM_0_RSTEN | \ + SRST_AARM_L2_0_RSTEN) + +#define ACPU_SC_RSTDIS (ACPU_CTRL_BASE + 0x01c) +#define ACPU_SC_RST_STAT (ACPU_CTRL_BASE + 0x020) +#define ACPU_SC_PDBGUP_MBIST (ACPU_CTRL_BASE + 0x02c) +#define PDBGUP_CLUSTER1_SHIFT 8 + +#define ACPU_SC_VD_CTRL (ACPU_CTRL_BASE + 0x054) +#define ACPU_SC_VD_MASK_PATTERN_CTRL (ACPU_CTRL_BASE + 0x058) +#define ACPU_SC_VD_MASK_PATTERN_VAL (0xCCB << 12) +#define ACPU_SC_VD_MASK_PATTERN_MASK ((0x1 << 13) - 1) + +#define ACPU_SC_VD_DLY_FIXED_CTRL (ACPU_CTRL_BASE + 0x05c) +#define ACPU_SC_VD_DLY_TABLE0_CTRL (ACPU_CTRL_BASE + 0x060) +#define ACPU_SC_VD_DLY_TABLE1_CTRL (ACPU_CTRL_BASE + 0x064) +#define ACPU_SC_VD_DLY_TABLE2_CTRL (ACPU_CTRL_BASE + 0x068) +#define ACPU_SC_VD_HPM_CTRL (ACPU_CTRL_BASE + 0x06c) +#define ACPU_SC_A53_CLUSTER_MTCMOS_EN (ACPU_CTRL_BASE + 0x088) +#define PW_MTCMOS_EN_A53_1_EN (1 << 1) +#define PW_MTCMOS_EN_A53_0_EN (1 << 0) + +#define ACPU_SC_A53_CLUSTER_MTCMOS_STA (ACPU_CTRL_BASE + 0x090) +#define ACPU_SC_A53_CLUSTER_ISO_EN (ACPU_CTRL_BASE + 0x098) +#define PW_ISO_A53_1_EN (1 << 1) +#define PW_ISO_A53_0_EN (1 << 0) + +#define ACPU_SC_A53_CLUSTER_ISO_DIS (ACPU_CTRL_BASE + 0x09c) +#define ACPU_SC_A53_CLUSTER_ISO_STA (ACPU_CTRL_BASE + 0x0a0) +#define ACPU_SC_A53_1_MTCMOS_TIMER (ACPU_CTRL_BASE + 0x0b4) +#define ACPU_SC_A53_0_MTCMOS_TIMER (ACPU_CTRL_BASE + 0x0bc) +#define ACPU_SC_A53_x_MTCMOS_TIMER(x) ((x) ? ACPU_SC_A53_1_MTCMOS_TIMER : ACPU_SC_A53_0_MTCMOS_TIMER) + +#define ACPU_SC_CPU0_CTRL (ACPU_CTRL_BASE + 0x100) +#define CPU_CTRL_AARCH64_MODE (1 << 7) + +#define ACPU_SC_CPU0_STAT (ACPU_CTRL_BASE + 0x104) +#define ACPU_SC_CPU0_CLKEN (ACPU_CTRL_BASE + 0x108) +#define CPU_CLKEN_HPM (1 << 1) + +#define ACPU_SC_CPU0_CLK_STAT (ACPU_CTRL_BASE + 0x110) + +#define ACPU_SC_CPU0_RSTEN (ACPU_CTRL_BASE + 0x114) +#define ACPU_SC_CPU0_RSTDIS (ACPU_CTRL_BASE + 0x118) +#define ACPU_SC_CPU0_MTCMOS_EN (ACPU_CTRL_BASE + 0x120) +#define CPU_MTCMOS_PW (1 << 0) + +#define ACPU_SC_CPU0_PW_ISOEN (ACPU_CTRL_BASE + 0x130) +#define CPU_PW_ISO (1 << 0) + +#define ACPU_SC_CPU0_PW_ISODIS (ACPU_CTRL_BASE + 0x134) +#define ACPU_SC_CPU0_PW_ISO_STAT (ACPU_CTRL_BASE + 0x138) +#define ACPU_SC_CPU0_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x154) +#define CPU_MTCMOS_TIMER_STA (1 << 0) + +#define ACPU_SC_CPU0_RVBARADDR (ACPU_CTRL_BASE + 0x158) +#define ACPU_SC_CPU1_CTRL (ACPU_CTRL_BASE + 0x200) +#define ACPU_SC_CPU1_STAT (ACPU_CTRL_BASE + 0x204) +#define ACPU_SC_CPU1_CLKEN (ACPU_CTRL_BASE + 0x208) +#define ACPU_SC_CPU1_CLK_STAT (ACPU_CTRL_BASE + 0x210) +#define ACPU_SC_CPU1_RSTEN (ACPU_CTRL_BASE + 0x214) +#define ACPU_SC_CPU1_RSTDIS (ACPU_CTRL_BASE + 0x218) +#define ACPU_SC_CPU1_MTCMOS_EN (ACPU_CTRL_BASE + 0x220) +#define ACPU_SC_CPU1_PW_ISODIS (ACPU_CTRL_BASE + 0x234) +#define ACPU_SC_CPU1_PW_ISO_STAT (ACPU_CTRL_BASE + 0x238) +#define ACPU_SC_CPU1_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x254) +#define ACPU_SC_CPU1_RVBARADDR (ACPU_CTRL_BASE + 0x258) +#define ACPU_SC_CPU2_CTRL (ACPU_CTRL_BASE + 0x300) +#define ACPU_SC_CPU2_STAT (ACPU_CTRL_BASE + 0x304) +#define ACPU_SC_CPU2_CLKEN (ACPU_CTRL_BASE + 0x308) +#define ACPU_SC_CPU2_CLK_STAT (ACPU_CTRL_BASE + 0x310) +#define ACPU_SC_CPU2_RSTEN (ACPU_CTRL_BASE + 0x314) +#define ACPU_SC_CPU2_RSTDIS (ACPU_CTRL_BASE + 0x318) +#define ACPU_SC_CPU2_MTCMOS_EN (ACPU_CTRL_BASE + 0x320) +#define ACPU_SC_CPU2_PW_ISODIS (ACPU_CTRL_BASE + 0x334) +#define ACPU_SC_CPU2_PW_ISO_STAT (ACPU_CTRL_BASE + 0x338) +#define ACPU_SC_CPU2_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x354) +#define ACPU_SC_CPU2_RVBARADDR (ACPU_CTRL_BASE + 0x358) +#define ACPU_SC_CPU3_CTRL (ACPU_CTRL_BASE + 0x400) +#define ACPU_SC_CPU3_STAT (ACPU_CTRL_BASE + 0x404) +#define ACPU_SC_CPU3_CLKEN (ACPU_CTRL_BASE + 0x408) +#define ACPU_SC_CPU3_CLK_STAT (ACPU_CTRL_BASE + 0x410) +#define ACPU_SC_CPU3_RSTEN (ACPU_CTRL_BASE + 0x414) +#define ACPU_SC_CPU3_RSTDIS (ACPU_CTRL_BASE + 0x418) +#define ACPU_SC_CPU3_MTCMOS_EN (ACPU_CTRL_BASE + 0x420) +#define ACPU_SC_CPU3_PW_ISODIS (ACPU_CTRL_BASE + 0x434) +#define ACPU_SC_CPU3_PW_ISO_STAT (ACPU_CTRL_BASE + 0x438) +#define ACPU_SC_CPU3_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x454) +#define ACPU_SC_CPU3_RVBARADDR (ACPU_CTRL_BASE + 0x458) +#define ACPU_SC_CPU4_CTRL (ACPU_CTRL_BASE + 0x500) +#define ACPU_SC_CPU4_STAT (ACPU_CTRL_BASE + 0x504) +#define ACPU_SC_CPU4_CLKEN (ACPU_CTRL_BASE + 0x508) +#define ACPU_SC_CPU4_CLK_STAT (ACPU_CTRL_BASE + 0x510) +#define ACPU_SC_CPU4_RSTEN (ACPU_CTRL_BASE + 0x514) +#define ACPU_SC_CPU4_RSTDIS (ACPU_CTRL_BASE + 0x518) +#define ACPU_SC_CPU4_MTCMOS_EN (ACPU_CTRL_BASE + 0x520) +#define ACPU_SC_CPU4_PW_ISODIS (ACPU_CTRL_BASE + 0x534) +#define ACPU_SC_CPU4_PW_ISO_STAT (ACPU_CTRL_BASE + 0x538) +#define ACPU_SC_CPU4_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x554) +#define ACPU_SC_CPU4_RVBARADDR (ACPU_CTRL_BASE + 0x558) +#define ACPU_SC_CPU5_CTRL (ACPU_CTRL_BASE + 0x600) +#define ACPU_SC_CPU5_STAT (ACPU_CTRL_BASE + 0x604) +#define ACPU_SC_CPU5_CLKEN (ACPU_CTRL_BASE + 0x608) +#define ACPU_SC_CPU5_CLK_STAT (ACPU_CTRL_BASE + 0x610) +#define ACPU_SC_CPU5_RSTEN (ACPU_CTRL_BASE + 0x614) +#define ACPU_SC_CPU5_RSTDIS (ACPU_CTRL_BASE + 0x618) +#define ACPU_SC_CPU5_MTCMOS_EN (ACPU_CTRL_BASE + 0x620) +#define ACPU_SC_CPU5_PW_ISODIS (ACPU_CTRL_BASE + 0x634) +#define ACPU_SC_CPU5_PW_ISO_STAT (ACPU_CTRL_BASE + 0x638) +#define ACPU_SC_CPU5_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x654) +#define ACPU_SC_CPU5_RVBARADDR (ACPU_CTRL_BASE + 0x658) +#define ACPU_SC_CPU6_CTRL (ACPU_CTRL_BASE + 0x700) +#define ACPU_SC_CPU6_STAT (ACPU_CTRL_BASE + 0x704) +#define ACPU_SC_CPU6_CLKEN (ACPU_CTRL_BASE + 0x708) +#define ACPU_SC_CPU6_CLK_STAT (ACPU_CTRL_BASE + 0x710) +#define ACPU_SC_CPU6_RSTEN (ACPU_CTRL_BASE + 0x714) +#define ACPU_SC_CPU6_RSTDIS (ACPU_CTRL_BASE + 0x718) +#define ACPU_SC_CPU6_MTCMOS_EN (ACPU_CTRL_BASE + 0x720) +#define ACPU_SC_CPU6_PW_ISODIS (ACPU_CTRL_BASE + 0x734) +#define ACPU_SC_CPU6_PW_ISO_STAT (ACPU_CTRL_BASE + 0x738) +#define ACPU_SC_CPU6_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x754) +#define ACPU_SC_CPU6_RVBARADDR (ACPU_CTRL_BASE + 0x758) +#define ACPU_SC_CPU7_CTRL (ACPU_CTRL_BASE + 0x800) +#define ACPU_SC_CPU7_STAT (ACPU_CTRL_BASE + 0x804) +#define ACPU_SC_CPU7_CLKEN (ACPU_CTRL_BASE + 0x808) +#define ACPU_SC_CPU7_CLK_STAT (ACPU_CTRL_BASE + 0x810) +#define ACPU_SC_CPU7_RSTEN (ACPU_CTRL_BASE + 0x814) +#define ACPU_SC_CPU7_RSTDIS (ACPU_CTRL_BASE + 0x818) +#define ACPU_SC_CPU7_MTCMOS_EN (ACPU_CTRL_BASE + 0x820) +#define ACPU_SC_CPU7_PW_ISODIS (ACPU_CTRL_BASE + 0x834) +#define ACPU_SC_CPU7_PW_ISO_STAT (ACPU_CTRL_BASE + 0x838) +#define ACPU_SC_CPU7_MTCMOS_TIMER_STAT (ACPU_CTRL_BASE + 0x854) +#define ACPU_SC_CPU7_RVBARADDR (ACPU_CTRL_BASE + 0x858) +#define ACPU_SC_CPUx_CTRL(x) ((x < 8) ? (ACPU_SC_CPU0_CTRL + 0x100 * x) : ACPU_SC_CPU0_CTRL) +#define ACPU_SC_CPUx_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_STAT + 0x100 * x) : ACPU_SC_CPU0_STAT) +#define ACPU_SC_CPUx_CLKEN(x) ((x < 8) ? (ACPU_SC_CPU0_CLKEN + 0x100 * x) : ACPU_SC_CPU0_CLKEN) +#define ACPU_SC_CPUx_CLK_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_CLK_STAT + 0x100 *x) : ACPU_SC_CPU0_CLK_STAT) +#define ACPU_SC_CPUx_RSTEN(x) ((x < 8) ? (ACPU_SC_CPU0_RSTEN + 0x100 * x) : ACPU_SC_CPU0_RSTEN) +#define ACPU_SC_CPUx_RSTDIS(x) ((x < 8) ? (ACPU_SC_CPU0_RSTDIS + 0x100 * x) : ACPU_SC_CPU0_RSTDIS) +#define ACPU_SC_CPUx_MTCMOS_EN(x) ((x < 8) ? (ACPU_SC_CPU0_MTCMOS_EN + 0x100 * x) : ACPU_SC_CPU0_MTCMOS_EN) +#define ACPU_SC_CPUx_PW_ISODIS(x) ((x < 8) ? (ACPU_SC_CPU0_PW_ISODIS + 0x100 * x) : ACPU_SC_CPU0_PW_ISODIS) +#define ACPU_SC_CPUx_PW_ISO_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_PW_ISO_STAT + 0x100 * x) : ACPU_SC_CPU0_PW_ISO_STAT) +#define ACPU_SC_CPUx_MTCMOS_TIMER_STAT(x) ((x < 8) ? (ACPU_SC_CPU0_MTCMOS_TIMER_STAT + 0x100 * x) : ACPU_SC_CPU0_MTCMOS_TIMER_STAT) +#define ACPU_SC_CPUx_RVBARADDR(x) ((x < 8) ? (ACPU_SC_CPU0_RVBARADDR + 0x100 * x) : ACPU_SC_CPU0_RVBARADDR) + +#define ACPU_SC_CPU_STAT_CLKDIV_VD_MASK (3 << 20) + +#define ACPU_SC_VD_CTRL_TUNE_EN_DIF (1 << 0) +#define ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT (0) +#define ACPU_SC_VD_CTRL_TUNE (1 << 1) +#define ACPU_SC_VD_CTRL_TUNE_SHIFT (1) +#define ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF (1 << 7) +#define ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT (7) +#define ACPU_SC_VD_CTRL_CALIBRATE_EN_INI (1 << 8) +#define ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT (8) +#define ACPU_SC_VD_CTRL_CLK_DIS_CNT_CLR (1 << 9) +#define ACPU_SC_VD_CTRL_CLK_DIS_CNT_CLR_SHIFT (9) +#define ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN (1 << 10) +#define ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT (10) +#define ACPU_SC_VD_CTRL_TUNE_EN_INT (1 << 11) +#define ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT (11) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE0 (1 << 12) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE0_MASK (0xf << 12) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT (12) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE1 (1 << 16) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE1_MASK (0xf << 16) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT (16) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE2 (1 << 20) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE2_MASK (0xf << 20) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT (20) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE3 (1 << 24) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE3_MASK (0xf << 24) +#define ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT (24) +#define ACPU_SC_VD_CTRL_FORCE_CLK_EN (1 << 28) +#define ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT (28) +#define ACPU_SC_VD_CTRL_DIV_EN_DIF (1 << 29) +#define ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT (29) + +#define ACPU_SC_VD_SHIFT_TABLE_TUNE_VAL \ + ((0x1 << ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT) | \ + (0x3 << ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT) | \ + (0x5 << ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT) | \ + (0x6 << ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT) | \ + (0x7 << ACPU_SC_VD_CTRL_TUNE_SHIFT)) + +#define ACPU_SC_VD_SHIFT_TABLE_TUNE_MASK \ + ((0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE0_SHIFT) | \ + (0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE1_SHIFT) | \ + (0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE2_SHIFT) | \ + (0xF << ACPU_SC_VD_CTRL_SHIFT_TABLE3_SHIFT) | \ + (0x3F << ACPU_SC_VD_CTRL_TUNE_SHIFT)) + +#define ACPU_SC_VD_HPM_CTRL_OSC_DIV (1 << 0) +#define ACPU_SC_VD_HPM_CTRL_OSC_DIV_SHIFT (0) +#define ACPU_SC_VD_HPM_CTRL_OSC_DIV_MASK (0x000000FF) +#define ACPU_SC_VD_HPM_CTRL_DLY_EXP (1 << 8) +#define ACPU_SC_VD_HPM_CTRL_DLY_EXP_SHIFT (8) +#define ACPU_SC_VD_HPM_CTRL_DLY_EXP_MASK (0x001FFF00) + +#define HPM_OSC_DIV_VAL \ + (0x56 << ACPU_SC_VD_HPM_CTRL_OSC_DIV_SHIFT) +#define HPM_OSC_DIV_MASK \ + (ACPU_SC_VD_HPM_CTRL_OSC_DIV_MASK) + +#define HPM_DLY_EXP_VAL \ + (0xC7A << ACPU_SC_VD_HPM_CTRL_DLY_EXP_SHIFT) +#define HPM_DLY_EXP_MASK \ + (ACPU_SC_VD_HPM_CTRL_DLY_EXP_MASK) + +#define ACPU_SC_VD_EN_ASIC_VAL \ + ((0x0 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \ + (0x0 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \ + (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \ + (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \ + (0X0 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \ + (0X0 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \ + (0x0 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT)) + +#define ACPU_SC_VD_EN_SFT_VAL \ + ((0x0 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \ + (0x0 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \ + (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \ + (0x0 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \ + (0x0 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \ + (0x0 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \ + (0x0 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT)) + +#define ACPU_SC_VD_EN_MASK \ + ((0x1 << ACPU_SC_VD_CTRL_FORCE_CLK_EN_SHIFT) | \ + (0x1 << ACPU_SC_VD_CTRL_CLK_DIS_CNT_EN_SHIFT) | \ + (0x1 << ACPU_SC_VD_CTRL_CALIBRATE_EN_INI_SHIFT) | \ + (0x1 << ACPU_SC_VD_CTRL_CALIBRATE_EN_DIF_SHIFT) | \ + (0x1 << ACPU_SC_VD_CTRL_DIV_EN_DIF_SHIFT) | \ + (0x1 << ACPU_SC_VD_CTRL_TUNE_EN_INT_SHIFT) | \ + (0x1 << ACPU_SC_VD_CTRL_TUNE_EN_DIF_SHIFT)) + +#endif /* __HI6220_REGS_ACPU_H__ */ diff --git a/plat/hikey/include/hi6220_regs_ao.h b/plat/hikey/include/hi6220_regs_ao.h new file mode 100644 index 0000000..1ee3468 --- /dev/null +++ b/plat/hikey/include/hi6220_regs_ao.h @@ -0,0 +1,357 @@ +/* + * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. + * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __HI6220_AO_H__ +#define __HI6220_AO_H__ + +#define AO_CTRL_BASE 0xF7800000 + +#define AO_SC_SYS_CTRL0 (AO_CTRL_BASE + 0x000) +#define AO_SC_SYS_CTRL1 (AO_CTRL_BASE + 0x004) +#define AO_SC_SYS_CTRL2 (AO_CTRL_BASE + 0x008) +#define AO_SC_SYS_STAT0 (AO_CTRL_BASE + 0x010) +#define AO_SC_SYS_STAT1 (AO_CTRL_BASE + 0x014) +#define AO_SC_MCU_IMCTRL (AO_CTRL_BASE + 0x018) +#define AO_SC_MCU_IMSTAT (AO_CTRL_BASE + 0x01C) +#define AO_SC_SECONDRY_INT_EN0 (AO_CTRL_BASE + 0x044) +#define AO_SC_SECONDRY_INT_STATR0 (AO_CTRL_BASE + 0x048) +#define AO_SC_SECONDRY_INT_STATM0 (AO_CTRL_BASE + 0x04C) +#define AO_SC_MCU_WKUP_INT_EN6 (AO_CTRL_BASE + 0x054) +#define AO_SC_MCU_WKUP_INT_STATR6 (AO_CTRL_BASE + 0x058) +#define AO_SC_MCU_WKUP_INT_STATM6 (AO_CTRL_BASE + 0x05C) +#define AO_SC_MCU_WKUP_INT_EN5 (AO_CTRL_BASE + 0x064) +#define AO_SC_MCU_WKUP_INT_STATR5 (AO_CTRL_BASE + 0x068) +#define AO_SC_MCU_WKUP_INT_STATM5 (AO_CTRL_BASE + 0x06C) +#define AO_SC_MCU_WKUP_INT_EN4 (AO_CTRL_BASE + 0x094) +#define AO_SC_MCU_WKUP_INT_STATR4 (AO_CTRL_BASE + 0x098) +#define AO_SC_MCU_WKUP_INT_STATM4 (AO_CTRL_BASE + 0x09C) +#define AO_SC_MCU_WKUP_INT_EN0 (AO_CTRL_BASE + 0x0A8) +#define AO_SC_MCU_WKUP_INT_STATR0 (AO_CTRL_BASE + 0x0AC) +#define AO_SC_MCU_WKUP_INT_STATM0 (AO_CTRL_BASE + 0x0B0) +#define AO_SC_MCU_WKUP_INT_EN1 (AO_CTRL_BASE + 0x0B4) +#define AO_SC_MCU_WKUP_INT_STATR1 (AO_CTRL_BASE + 0x0B8) +#define AO_SC_MCU_WKUP_INT_STATM1 (AO_CTRL_BASE + 0x0BC) +#define AO_SC_INT_STATR (AO_CTRL_BASE + 0x0C4) +#define AO_SC_INT_STATM (AO_CTRL_BASE + 0x0C8) +#define AO_SC_INT_CLEAR (AO_CTRL_BASE + 0x0CC) +#define AO_SC_INT_EN_SET (AO_CTRL_BASE + 0x0D0) +#define AO_SC_INT_EN_DIS (AO_CTRL_BASE + 0x0D4) +#define AO_SC_INT_EN_STAT (AO_CTRL_BASE + 0x0D8) +#define AO_SC_INT_STATR1 (AO_CTRL_BASE + 0x0E4) +#define AO_SC_INT_STATM1 (AO_CTRL_BASE + 0x0E8) +#define AO_SC_INT_CLEAR1 (AO_CTRL_BASE + 0x0EC) +#define AO_SC_INT_EN_SET1 (AO_CTRL_BASE + 0x0F0) +#define AO_SC_INT_EN_DIS1 (AO_CTRL_BASE + 0x0F4) +#define AO_SC_INT_EN_STAT1 (AO_CTRL_BASE + 0x0F8) +#define AO_SC_TIMER_EN0 (AO_CTRL_BASE + 0x1D0) +#define AO_SC_TIMER_EN1 (AO_CTRL_BASE + 0x1D4) +#define AO_SC_TIMER_EN4 (AO_CTRL_BASE + 0x1F0) +#define AO_SC_TIMER_EN5 (AO_CTRL_BASE + 0x1F4) +#define AO_SC_MCU_SUBSYS_CTRL0 (AO_CTRL_BASE + 0x400) +#define AO_SC_MCU_SUBSYS_CTRL1 (AO_CTRL_BASE + 0x404) +#define AO_SC_MCU_SUBSYS_CTRL2 (AO_CTRL_BASE + 0x408) +#define AO_SC_MCU_SUBSYS_CTRL3 (AO_CTRL_BASE + 0x40C) +#define AO_SC_MCU_SUBSYS_CTRL4 (AO_CTRL_BASE + 0x410) +#define AO_SC_MCU_SUBSYS_CTRL5 (AO_CTRL_BASE + 0x414) +#define AO_SC_MCU_SUBSYS_CTRL6 (AO_CTRL_BASE + 0x418) +#define AO_SC_MCU_SUBSYS_CTRL7 (AO_CTRL_BASE + 0x41C) +#define AO_SC_MCU_SUBSYS_STAT0 (AO_CTRL_BASE + 0x440) +#define AO_SC_MCU_SUBSYS_STAT1 (AO_CTRL_BASE + 0x444) +#define AO_SC_MCU_SUBSYS_STAT2 (AO_CTRL_BASE + 0x448) +#define AO_SC_MCU_SUBSYS_STAT3 (AO_CTRL_BASE + 0x44C) +#define AO_SC_MCU_SUBSYS_STAT4 (AO_CTRL_BASE + 0x450) +#define AO_SC_MCU_SUBSYS_STAT5 (AO_CTRL_BASE + 0x454) +#define AO_SC_MCU_SUBSYS_STAT6 (AO_CTRL_BASE + 0x458) +#define AO_SC_MCU_SUBSYS_STAT7 (AO_CTRL_BASE + 0x45C) +#define AO_SC_PERIPH_CLKEN4 (AO_CTRL_BASE + 0x630) +#define AO_SC_PERIPH_CLKDIS4 (AO_CTRL_BASE + 0x634) +#define AO_SC_PERIPH_CLKSTAT4 (AO_CTRL_BASE + 0x638) +#define AO_SC_PERIPH_CLKEN5 (AO_CTRL_BASE + 0x63C) +#define AO_SC_PERIPH_CLKDIS5 (AO_CTRL_BASE + 0x640) +#define AO_SC_PERIPH_CLKSTAT5 (AO_CTRL_BASE + 0x644) +#define AO_SC_PERIPH_RSTEN4 (AO_CTRL_BASE + 0x6F0) +#define AO_SC_PERIPH_RSTDIS4 (AO_CTRL_BASE + 0x6F4) +#define AO_SC_PERIPH_RSTSTAT4 (AO_CTRL_BASE + 0x6F8) +#define AO_SC_PERIPH_RSTEN5 (AO_CTRL_BASE + 0x6FC) +#define AO_SC_PERIPH_RSTDIS5 (AO_CTRL_BASE + 0x700) +#define AO_SC_PERIPH_RSTSTAT5 (AO_CTRL_BASE + 0x704) +#define AO_SC_PW_CLKEN0 (AO_CTRL_BASE + 0x800) +#define AO_SC_PW_CLKDIS0 (AO_CTRL_BASE + 0x804) +#define AO_SC_PW_CLK_STAT0 (AO_CTRL_BASE + 0x808) +#define AO_SC_PW_RSTEN0 (AO_CTRL_BASE + 0x810) +#define AO_SC_PW_RSTDIS0 (AO_CTRL_BASE + 0x814) +#define AO_SC_PW_RST_STAT0 (AO_CTRL_BASE + 0x818) +#define AO_SC_PW_ISOEN0 (AO_CTRL_BASE + 0x820) +#define AO_SC_PW_ISODIS0 (AO_CTRL_BASE + 0x824) +#define AO_SC_PW_ISO_STAT0 (AO_CTRL_BASE + 0x828) +#define AO_SC_PW_MTCMOS_EN0 (AO_CTRL_BASE + 0x830) +#define AO_SC_PW_MTCMOS_DIS0 (AO_CTRL_BASE + 0x834) +#define AO_SC_PW_MTCMOS_STAT0 (AO_CTRL_BASE + 0x838) +#define AO_SC_PW_MTCMOS_ACK_STAT0 (AO_CTRL_BASE + 0x83C) +#define AO_SC_PW_MTCMOS_TIMEOUT_STAT0 (AO_CTRL_BASE + 0x840) +#define AO_SC_PW_STAT0 (AO_CTRL_BASE + 0x850) +#define AO_SC_PW_STAT1 (AO_CTRL_BASE + 0x854) +#define AO_SC_SYSTEST_STAT (AO_CTRL_BASE + 0x880) +#define AO_SC_SYSTEST_SLICER_CNT0 (AO_CTRL_BASE + 0x890) +#define AO_SC_SYSTEST_SLICER_CNT1 (AO_CTRL_BASE + 0x894) +#define AO_SC_PW_CTRL1 (AO_CTRL_BASE + 0x8C8) +#define AO_SC_PW_CTRL (AO_CTRL_BASE + 0x8CC) +#define AO_SC_MCPU_VOTEEN (AO_CTRL_BASE + 0x8D0) +#define AO_SC_MCPU_VOTEDIS (AO_CTRL_BASE + 0x8D4) +#define AO_SC_MCPU_VOTESTAT (AO_CTRL_BASE + 0x8D8) +#define AO_SC_MCPU_VOTE_MSK0 (AO_CTRL_BASE + 0x8E0) +#define AO_SC_MCPU_VOTE_MSK1 (AO_CTRL_BASE + 0x8E4) +#define AO_SC_MCPU_VOTESTAT0_MSK (AO_CTRL_BASE + 0x8E8) +#define AO_SC_MCPU_VOTESTAT1_MSK (AO_CTRL_BASE + 0x8EC) +#define AO_SC_PERI_VOTEEN (AO_CTRL_BASE + 0x8F0) +#define AO_SC_PERI_VOTEDIS (AO_CTRL_BASE + 0x8F4) +#define AO_SC_PERI_VOTESTAT (AO_CTRL_BASE + 0x8F8) +#define AO_SC_PERI_VOTE_MSK0 (AO_CTRL_BASE + 0x900) +#define AO_SC_PERI_VOTE_MSK1 (AO_CTRL_BASE + 0x904) +#define AO_SC_PERI_VOTESTAT0_MSK (AO_CTRL_BASE + 0x908) +#define AO_SC_PERI_VOTESTAT1_MSK (AO_CTRL_BASE + 0x90C) +#define AO_SC_ACPU_VOTEEN (AO_CTRL_BASE + 0x910) +#define AO_SC_ACPU_VOTEDIS (AO_CTRL_BASE + 0x914) +#define AO_SC_ACPU_VOTESTAT (AO_CTRL_BASE + 0x918) +#define AO_SC_ACPU_VOTE_MSK0 (AO_CTRL_BASE + 0x920) +#define AO_SC_ACPU_VOTE_MSK1 (AO_CTRL_BASE + 0x924) +#define AO_SC_ACPU_VOTESTAT0_MSK (AO_CTRL_BASE + 0x928) +#define AO_SC_ACPU_VOTESTAT1_MSK (AO_CTRL_BASE + 0x92C) +#define AO_SC_MCU_VOTEEN (AO_CTRL_BASE + 0x930) +#define AO_SC_MCU_VOTEDIS (AO_CTRL_BASE + 0x934) +#define AO_SC_MCU_VOTESTAT (AO_CTRL_BASE + 0x938) +#define AO_SC_MCU_VOTE_MSK0 (AO_CTRL_BASE + 0x940) +#define AO_SC_MCU_VOTE_MSK1 (AO_CTRL_BASE + 0x944) +#define AO_SC_MCU_VOTESTAT0_MSK (AO_CTRL_BASE + 0x948) +#define AO_SC_MCU_VOTESTAT1_MSK (AO_CTRL_BASE + 0x94C) +#define AO_SC_MCU_VOTE1EN (AO_CTRL_BASE + 0x960) +#define AO_SC_MCU_VOTE1DIS (AO_CTRL_BASE + 0x964) +#define AO_SC_MCU_VOTE1STAT (AO_CTRL_BASE + 0x968) +#define AO_SC_MCU_VOTE1_MSK0 (AO_CTRL_BASE + 0x970) +#define AO_SC_MCU_VOTE1_MSK1 (AO_CTRL_BASE + 0x974) +#define AO_SC_MCU_VOTE1STAT0_MSK (AO_CTRL_BASE + 0x978) +#define AO_SC_MCU_VOTE1STAT1_MSK (AO_CTRL_BASE + 0x97C) +#define AO_SC_MCU_VOTE2EN (AO_CTRL_BASE + 0x980) +#define AO_SC_MCU_VOTE2DIS (AO_CTRL_BASE + 0x984) +#define AO_SC_MCU_VOTE2STAT (AO_CTRL_BASE + 0x988) +#define AO_SC_MCU_VOTE2_MSK0 (AO_CTRL_BASE + 0x990) +#define AO_SC_MCU_VOTE2_MSK1 (AO_CTRL_BASE + 0x994) +#define AO_SC_MCU_VOTE2STAT0_MSK (AO_CTRL_BASE + 0x998) +#define AO_SC_MCU_VOTE2STAT1_MSK (AO_CTRL_BASE + 0x99C) +#define AO_SC_VOTE_CTRL (AO_CTRL_BASE + 0x9A0) +#define AO_SC_VOTE_STAT (AO_CTRL_BASE + 0x9A4) +#define AO_SC_ECONUM (AO_CTRL_BASE + 0xF00) +#define AO_SCCHIPID (AO_CTRL_BASE + 0xF10) +#define AO_SCSOCID (AO_CTRL_BASE + 0xF1C) +#define AO_SC_SOC_FPGA_RTL_DEF (AO_CTRL_BASE + 0xFE0) +#define AO_SC_SOC_FPGA_PR_DEF (AO_CTRL_BASE + 0xFE4) +#define AO_SC_SOC_FPGA_RES_DEF0 (AO_CTRL_BASE + 0xFE8) +#define AO_SC_SOC_FPGA_RES_DEF1 (AO_CTRL_BASE + 0xFEC) +#define AO_SC_XTAL_CTRL0 (AO_CTRL_BASE + 0x102) +#define AO_SC_XTAL_CTRL1 (AO_CTRL_BASE + 0x102) +#define AO_SC_XTAL_CTRL3 (AO_CTRL_BASE + 0x103) +#define AO_SC_XTAL_CTRL5 (AO_CTRL_BASE + 0x103) +#define AO_SC_XTAL_STAT0 (AO_CTRL_BASE + 0x106) +#define AO_SC_XTAL_STAT1 (AO_CTRL_BASE + 0x107) +#define AO_SC_EFUSE_CHIPID0 (AO_CTRL_BASE + 0x108) +#define AO_SC_EFUSE_CHIPID1 (AO_CTRL_BASE + 0x108) +#define AO_SC_EFUSE_SYS_CTRL (AO_CTRL_BASE + 0x108) +#define AO_SC_DEBUG_CTRL1 (AO_CTRL_BASE + 0x128) +#define AO_SC_DBG_STAT (AO_CTRL_BASE + 0x12B) +#define AO_SC_ARM_DBG_KEY0 (AO_CTRL_BASE + 0x12B) +#define AO_SC_RESERVED31 (AO_CTRL_BASE + 0x13A) +#define AO_SC_RESERVED32 (AO_CTRL_BASE + 0x13A) +#define AO_SC_RESERVED33 (AO_CTRL_BASE + 0x13A) +#define AO_SC_RESERVED34 (AO_CTRL_BASE + 0x13A) +#define AO_SC_RESERVED35 (AO_CTRL_BASE + 0x13B) +#define AO_SC_RESERVED36 (AO_CTRL_BASE + 0x13B) +#define AO_SC_RESERVED37 (AO_CTRL_BASE + 0x13B) +#define AO_SC_RESERVED38 (AO_CTRL_BASE + 0x13B) +#define AO_SC_ALWAYSON_SYS_CTRL0 (AO_CTRL_BASE + 0x148) +#define AO_SC_ALWAYSON_SYS_CTRL1 (AO_CTRL_BASE + 0x148) +#define AO_SC_ALWAYSON_SYS_CTRL2 (AO_CTRL_BASE + 0x148) +#define AO_SC_ALWAYSON_SYS_CTRL3 (AO_CTRL_BASE + 0x148) +#define AO_SC_ALWAYSON_SYS_CTRL10 (AO_CTRL_BASE + 0x14A) +#define AO_SC_ALWAYSON_SYS_CTRL11 (AO_CTRL_BASE + 0x14A) +#define AO_SC_ALWAYSON_SYS_STAT0 (AO_CTRL_BASE + 0x14C) +#define AO_SC_ALWAYSON_SYS_STAT1 (AO_CTRL_BASE + 0x14C) +#define AO_SC_ALWAYSON_SYS_STAT2 (AO_CTRL_BASE + 0x14C) +#define AO_SC_ALWAYSON_SYS_STAT3 (AO_CTRL_BASE + 0x14C) +#define AO_SC_PWUP_TIME0 (AO_CTRL_BASE + 0x188) +#define AO_SC_PWUP_TIME1 (AO_CTRL_BASE + 0x188) +#define AO_SC_PWUP_TIME2 (AO_CTRL_BASE + 0x188) +#define AO_SC_PWUP_TIME3 (AO_CTRL_BASE + 0x188) +#define AO_SC_PWUP_TIME4 (AO_CTRL_BASE + 0x189) +#define AO_SC_PWUP_TIME5 (AO_CTRL_BASE + 0x189) +#define AO_SC_PWUP_TIME6 (AO_CTRL_BASE + 0x189) +#define AO_SC_PWUP_TIME7 (AO_CTRL_BASE + 0x189) +#define AO_SC_SECURITY_CTRL1 (AO_CTRL_BASE + 0x1C0) + +#define AO_SC_SYS_CTRL0_MODE_NORMAL 0x004 +#define AO_SC_SYS_CTRL0_MODE_MASK 0x007 + +#define AO_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0) +#define AO_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1) +#define AO_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2) +#define AO_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3) +#define AO_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4) +#define AO_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6) +#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7) +#define AO_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8) +#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9) +#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10) +#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11) +#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12) +#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13) +#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15) +#define AO_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16) +#define AO_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17) +#define AO_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18) +#define AO_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19) +#define AO_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20) +#define AO_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22) +#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23) +#define AO_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24) +#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25) +#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26) +#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27) +#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28) +#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29) +#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31) + +#define AO_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26) +#define AO_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27) +#define AO_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28) +#define AO_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29) +#define AO_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30) +#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31) + +#define AO_SC_SYS_STAT0_MCU_RST_STAT (1 << 25) +#define AO_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26) +#define AO_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27) +#define AO_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28) +#define AO_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29) +#define AO_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30) +#define AO_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31) + +#define AO_SC_SYS_STAT1_MODE_STATUS (1 << 0) +#define AO_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16) +#define AO_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17) +#define AO_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19) +#define AO_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20) +#define AO_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27) +#define AO_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28) +#define AO_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29) + +#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_ECTR_N (1 << 0) +#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_SYS_N (1 << 1) +#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_POR_N (1 << 2) +#define AO_SC_PERIPH_RSTDIS4_RESET_MCU_DAP_N (1 << 3) +#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_TIMER0_N (1 << 4) +#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_TIMER1_N (1 << 5) +#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_WDT0_N (1 << 6) +#define AO_SC_PERIPH_RSTDIS4_PRESET_CM3_WDT1_N (1 << 7) +#define AO_SC_PERIPH_RSTDIS4_HRESET_IPC_S_N (1 << 8) +#define AO_SC_PERIPH_RSTDIS4_HRESET_IPC_NS_N (1 << 9) +#define AO_SC_PERIPH_RSTDIS4_PRESET_EFUSEC_N (1 << 10) +#define AO_SC_PERIPH_RSTDIS4_PRESET_WDT0_N (1 << 12) +#define AO_SC_PERIPH_RSTDIS4_PRESET_WDT1_N (1 << 13) +#define AO_SC_PERIPH_RSTDIS4_PRESET_WDT2_N (1 << 14) +#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER0_N (1 << 15) +#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER1_N (1 << 16) +#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER2_N (1 << 17) +#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER3_N (1 << 18) +#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER4_N (1 << 19) +#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER5_N (1 << 20) +#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER6_N (1 << 21) +#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER7_N (1 << 22) +#define AO_SC_PERIPH_RSTDIS4_PRESET_TIMER8_N (1 << 23) +#define AO_SC_PERIPH_RSTDIS4_PRESET_UART0_N (1 << 24) +#define AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N (1 << 25) +#define AO_SC_PERIPH_RSTDIS4_RESET_RTC1_N (1 << 26) +#define AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N (1 << 27) +#define AO_SC_PERIPH_RSTDIS4_RESET_JTAG_AUTH_N (1 << 28) +#define AO_SC_PERIPH_RSTDIS4_RESET_CS_DAPB_ON_N (1 << 29) +#define AO_SC_PERIPH_RSTDIS4_MDM_SUBSYS_GLB (1 << 30) + +#define AO_SC_PERIPH_CLKEN4_HCLK_MCU (1 << 0) +#define AO_SC_PERIPH_CLKEN4_CLK_MCU_DAP (1 << 3) +#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_TIMER0 (1 << 4) +#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_TIMER1 (1 << 5) +#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_WDT0 (1 << 6) +#define AO_SC_PERIPH_CLKEN4_PCLK_CM3_WDT1 (1 << 7) +#define AO_SC_PERIPH_CLKEN4_HCLK_IPC_S (1 << 8) +#define AO_SC_PERIPH_CLKEN4_HCLK_IPC_NS (1 << 9) +#define AO_SC_PERIPH_CLKEN4_PCLK_EFUSEC (1 << 10) +#define AO_SC_PERIPH_CLKEN4_PCLK_TZPC (1 << 11) +#define AO_SC_PERIPH_CLKEN4_PCLK_WDT0 (1 << 12) +#define AO_SC_PERIPH_CLKEN4_PCLK_WDT1 (1 << 13) +#define AO_SC_PERIPH_CLKEN4_PCLK_WDT2 (1 << 14) +#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER0 (1 << 15) +#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER1 (1 << 16) +#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER2 (1 << 17) +#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER3 (1 << 18) +#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER4 (1 << 19) +#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER5 (1 << 20) +#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER6 (1 << 21) +#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER7 (1 << 22) +#define AO_SC_PERIPH_CLKEN4_PCLK_TIMER8 (1 << 23) +#define AO_SC_PERIPH_CLKEN4_CLK_UART0 (1 << 24) +#define AO_SC_PERIPH_CLKEN4_CLK_RTC0 (1 << 25) +#define AO_SC_PERIPH_CLKEN4_CLK_RTC1 (1 << 26) +#define AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI (1 << 27) +#define AO_SC_PERIPH_CLKEN4_CLK_JTAG_AUTH (1 << 28) +#define AO_SC_PERIPH_CLKEN4_CLK_CS_DAPB_ON (1 << 29) +#define AO_SC_PERIPH_CLKEN4_CLK_PDM (1 << 30) +#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD (1 << 31) + +#define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU (1 << 0) +#define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_CCPU (1 << 1) +#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_CCPU (1 << 2) +#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_NS_CCPU (1 << 3) +#define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU (1 << 16) +#define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_MCU (1 << 17) +#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_MCU (1 << 18) +#define AO_SC_PERIPH_CLKEN5_HCLK_IPC_NS_MCU (1 << 19) + +#define AO_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003 +#define AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007 +#define AO_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3) +#define AO_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4) +#define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8) +#define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9) +#define AO_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10) +#define AO_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11) + +#define PCLK_TIMER1 (1 << 16) +#define PCLK_TIMER0 (1 << 15) + +#endif /* __HI6220_AO_H__ */ diff --git a/plat/hikey/include/hi6220_regs_peri.h b/plat/hikey/include/hi6220_regs_peri.h new file mode 100644 index 0000000..9ce4128 --- /dev/null +++ b/plat/hikey/include/hi6220_regs_peri.h @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. + * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __HI6220_PERI_H__ +#define __HI6220_PERI_H__ + +#define PERI_BASE 0xF7030000 + +#define PERI_SC_PERIPH_CTRL1 (PERI_BASE + 0x000) +#define PERI_SC_PERIPH_CTRL2 (PERI_BASE + 0x004) +#define PERI_SC_PERIPH_CTRL3 (PERI_BASE + 0x008) +#define PERI_SC_PERIPH_CTRL4 (PERI_BASE + 0x00c) +#define PERI_SC_PERIPH_CTRL5 (PERI_BASE + 0x010) +#define PERI_SC_PERIPH_CTRL6 (PERI_BASE + 0x014) +#define PERI_SC_PERIPH_CTRL8 (PERI_BASE + 0x018) +#define PERI_SC_PERIPH_CTRL9 (PERI_BASE + 0x01c) +#define PERI_SC_PERIPH_CTRL10 (PERI_BASE + 0x020) +#define PERI_SC_PERIPH_CTRL12 (PERI_BASE + 0x024) +#define PERI_SC_PERIPH_CTRL13 (PERI_BASE + 0x028) +#define PERI_SC_PERIPH_CTRL14 (PERI_BASE + 0x02c) + +#define PERI_SC_DDR_CTRL0 (PERI_BASE + 0x050) +#define PERI_SC_PERIPH_STAT1 (PERI_BASE + 0x094) + +#define PERI_SC_PERIPH_CLKEN0 (PERI_BASE + 0x200) +#define PERI_SC_PERIPH_CLKDIS0 (PERI_BASE + 0x204) +#define PERI_SC_PERIPH_CLKSTAT0 (PERI_BASE + 0x208) +#define PERI_SC_PERIPH_CLKEN1 (PERI_BASE + 0x210) +#define PERI_SC_PERIPH_CLKDIS1 (PERI_BASE + 0x214) +#define PERI_SC_PERIPH_CLKSTAT1 (PERI_BASE + 0x218) +#define PERI_SC_PERIPH_CLKEN2 (PERI_BASE + 0x220) +#define PERI_SC_PERIPH_CLKDIS2 (PERI_BASE + 0x224) +#define PERI_SC_PERIPH_CLKSTAT2 (PERI_BASE + 0x228) +#define PERI_SC_PERIPH_CLKEN3 (PERI_BASE + 0x230) +#define PERI_SC_PERIPH_CLKDIS3 (PERI_BASE + 0x234) +#define PERI_SC_PERIPH_CLKSTAT3 (PERI_BASE + 0x238) +#define PERI_SC_PERIPH_CLKEN8 (PERI_BASE + 0x240) +#define PERI_SC_PERIPH_CLKDIS8 (PERI_BASE + 0x244) +#define PERI_SC_PERIPH_CLKSTAT8 (PERI_BASE + 0x248) +#define PERI_SC_PERIPH_CLKEN9 (PERI_BASE + 0x250) +#define PERI_SC_PERIPH_CLKDIS9 (PERI_BASE + 0x254) +#define PERI_SC_PERIPH_CLKSTAT9 (PERI_BASE + 0x258) +#define PERI_SC_PERIPH_CLKEN10 (PERI_BASE + 0x260) +#define PERI_SC_PERIPH_CLKDIS10 (PERI_BASE + 0x264) +#define PERI_SC_PERIPH_CLKSTAT10 (PERI_BASE + 0x268) +#define PERI_SC_PERIPH_CLKEN12 (PERI_BASE + 0x270) +#define PERI_SC_PERIPH_CLKDIS12 (PERI_BASE + 0x274) +#define PERI_SC_PERIPH_CLKSTAT12 (PERI_BASE + 0x278) + +#define PERI_SC_PERIPH_RSTEN0 (PERI_BASE + 0x300) +#define PERI_SC_PERIPH_RSTDIS0 (PERI_BASE + 0x304) +#define PERI_SC_PERIPH_RSTSTAT0 (PERI_BASE + 0x308) +#define PERI_SC_PERIPH_RSTEN1 (PERI_BASE + 0x310) +#define PERI_SC_PERIPH_RSTDIS1 (PERI_BASE + 0x314) +#define PERI_SC_PERIPH_RSTSTAT1 (PERI_BASE + 0x318) +#define PERI_SC_PERIPH_RSTEN2 (PERI_BASE + 0x320) +#define PERI_SC_PERIPH_RSTDIS2 (PERI_BASE + 0x324) +#define PERI_SC_PERIPH_RSTSTAT2 (PERI_BASE + 0x328) +#define PERI_SC_PERIPH_RSTEN3 (PERI_BASE + 0x330) +#define PERI_SC_PERIPH_RSTDIS3 (PERI_BASE + 0x334) +#define PERI_SC_PERIPH_RSTSTAT3 (PERI_BASE + 0x338) +#define PERI_SC_PERIPH_RSTEN8 (PERI_BASE + 0x340) +#define PERI_SC_PERIPH_RSTDIS8 (PERI_BASE + 0x344) +#define PERI_SC_PERIPH_RSTSTAT8 (PERI_BASE + 0x338) + +#define PERI_SC_CLK_SEL0 (PERI_BASE + 0x400) +#define PERI_SC_CLKCFG8BIT1 (PERI_BASE + 0x494) +#define PERI_SC_RESERVED8_ADDR (PERI_BASE + 0xd04) + +/* PERI_SC_PERIPH_CTRL1 */ +#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) +#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) +#define PERI_CTRL1_HIFI_INT_MASK (1 << 1) +#define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2) +#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16) +#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17) +#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18) + +/* PERI_SC_PERIPH_CTRL2 */ +#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0) +#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2) +#define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6) +#define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7) +#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8) +#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9) +#define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12) +#define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20) +#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22) +#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26) +#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27) +#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28) + +/* PERI_SC_PERIPH_CTRL3 */ +#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0) +#define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12) +#define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22) +#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24) + +/* PERI_SC_PERIPH_CTRL4 */ +#define PERI_CTRL4_PICO_FSELV (1 << 0) +#define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3) +#define PERI_CTRL4_PICO_REFCLKSEL (1 << 4) +#define PERI_CTRL4_PICO_SIDDQ (1 << 6) +#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7) +#define PERI_CTRL4_PICO_OGDISABLE (1 << 8) +#define PERI_CTRL4_PICO_COMMONONN (1 << 9) +#define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10) +#define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11) +#define PERI_CTRL4_PICO_VATESTENB (1 << 12) +#define PERI_CTRL4_PICO_SUSPENDM (1 << 14) +#define PERI_CTRL4_PICO_SLEEPM (1 << 15) +#define PERI_CTRL4_BC11_C (1 << 16) +#define PERI_CTRL4_BC11_B (1 << 17) +#define PERI_CTRL4_BC11_A (1 << 18) +#define PERI_CTRL4_BC11_GND (1 << 19) +#define PERI_CTRL4_BC11_FLOAT (1 << 20) +#define PERI_CTRL4_OTG_PHY_SEL (1 << 21) +#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22) +#define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24) +#define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25) +#define PERI_CTRL4_OTG_IDPULLUP (1 << 26) +#define PERI_CTRL4_OTG_DRVBUS (1 << 27) +#define PERI_CTRL4_OTG_SESSEND (1 << 28) +#define PERI_CTRL4_OTG_BVALID (1 << 29) +#define PERI_CTRL4_OTG_AVALID (1 << 30) +#define PERI_CTRL4_OTG_VBUSVALID (1 << 31) + +/* PERI_SC_PERIPH_CTRL5 */ +#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3) +#define PERI_CTRL5_PICOPHY_ACAENB (1 << 4) +#define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5) +#define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6) +#define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7) +#define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8) +#define PERI_CTRL5_PICOPHY_DCDENB (1 << 9) +#define PERI_CTRL5_PICOPHY_IDDIG (1 << 10) +#define PERI_CTRL5_DBG_MUX (1 << 11) + +/* PERI_SC_PERIPH_CTRL6 */ +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11) +#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12) + +/* PERI_SC_PERIPH_CTRL8 */ +#define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0) +#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2) +#define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4) +#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6) +#define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8) +#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11) +#define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12) +#define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16) +#define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20) +#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28) + +/* PERI_SC_PERIPH_CTRL9 */ +#define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0) +#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1) +#define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4) +#define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8) + +/* + * PERI_SC_PERIPH_CLKEN0 + * PERI_SC_PERIPH_CLKDIS0 + * PERI_SC_PERIPH_CLKSTAT0 + */ +#define PERI_CLK0_MMC0 (1 << 0) +#define PERI_CLK0_MMC1 (1 << 1) +#define PERI_CLK0_MMC2 (1 << 2) +#define PERI_CLK0_NANDC (1 << 3) +#define PERI_CLK0_USBOTG (1 << 4) +#define PERI_CLK0_PICOPHY (1 << 5) +#define PERI_CLK0_PLL (1 << 6) + +/* + * PERI_SC_PERIPH_CLKEN1 + * PERI_SC_PERIPH_CLKDIS1 + * PERI_SC_PERIPH_CLKSTAT1 + */ +#define PERI_CLK1_HIFI (1 << 0) +#define PERI_CLK1_DIGACODEC (1 << 5) + +/* + * PERI_SC_PERIPH_CLKEN2 + * PERI_SC_PERIPH_CLKDIS2 + * PERI_SC_PERIPH_CLKSTAT2 + */ +#define PERI_CLK2_IPF (1 << 0) +#define PERI_CLK2_SOCP (1 << 1) +#define PERI_CLK2_DMAC (1 << 2) +#define PERI_CLK2_SECENG (1 << 3) +#define PERI_CLK2_HPM0 (1 << 5) +#define PERI_CLK2_HPM1 (1 << 6) +#define PERI_CLK2_HPM2 (1 << 7) +#define PERI_CLK2_HPM3 (1 << 8) + +/* + * PERI_SC_PERIPH_CLKEN3 + * PERI_SC_PERIPH_CLKDIS3 + * PERI_SC_PERIPH_CLKSTAT3 + */ +#define PERI_CLK3_CSSYS (1 << 0) +#define PERI_CLK3_I2C0 (1 << 1) +#define PERI_CLK3_I2C1 (1 << 2) +#define PERI_CLK3_I2C2 (1 << 3) +#define PERI_CLK3_I2C3 (1 << 4) +#define PERI_CLK3_UART1 (1 << 5) +#define PERI_CLK3_UART2 (1 << 6) +#define PERI_CLK3_UART3 (1 << 7) +#define PERI_CLK3_UART4 (1 << 8) +#define PERI_CLK3_SSP (1 << 9) +#define PERI_CLK3_PWM (1 << 10) +#define PERI_CLK3_BLPWM (1 << 11) +#define PERI_CLK3_TSENSOR (1 << 12) +#define PERI_CLK3_GPS (1 << 15) +#define PERI_CLK3_TCXO_PAD0 (1 << 16) +#define PERI_CLK3_TCXO_PAD1 (1 << 17) +#define PERI_CLK3_DAPB (1 << 18) +#define PERI_CLK3_HKADC (1 << 19) +#define PERI_CLK3_CODEC_SSI (1 << 20) +#define PERI_CLK3_TZPC_DEP (1 << 21) + +/* + * PERI_SC_PERIPH_CLKEN8 + * PERI_SC_PERIPH_CLKDIS8 + * PERI_SC_PERIPH_CLKSTAT8 + */ +#define PERI_CLK8_RS0 (1 << 0) +#define PERI_CLK8_RS2 (1 << 1) +#define PERI_CLK8_RS3 (1 << 2) +#define PERI_CLK8_MS0 (1 << 3) +#define PERI_CLK8_MS2 (1 << 5) +#define PERI_CLK8_XG2RAM0 (1 << 6) +#define PERI_CLK8_X2SRAM (1 << 7) +#define PERI_CLK8_SRAM (1 << 8) +#define PERI_CLK8_ROM (1 << 9) +#define PERI_CLK8_HARQ (1 << 10) +#define PERI_CLK8_MMU (1 << 11) +#define PERI_CLK8_DDRC (1 << 12) +#define PERI_CLK8_DDRPHY (1 << 13) +#define PERI_CLK8_DDRPHY_REF (1 << 14) +#define PERI_CLK8_X2X_SYSNOC (1 << 15) +#define PERI_CLK8_X2X_CCPU (1 << 16) +#define PERI_CLK8_DDRT (1 << 17) +#define PERI_CLK8_DDRPACK_RS (1 << 18) + +/* + * PERI_SC_PERIPH_CLKEN9 + * PERI_SC_PERIPH_CLKDIS9 + * PERI_SC_PERIPH_CLKSTAT9 + */ +#define PERI_CLK9_CARM_DAP (1 << 0) +#define PERI_CLK9_CARM_ATB (1 << 1) +#define PERI_CLK9_CARM_LBUS (1 << 2) +#define PERI_CLK9_CARM_KERNEL (1 << 3) + +/* + * PERI_SC_PERIPH_CLKEN10 + * PERI_SC_PERIPH_CLKDIS10 + * PERI_SC_PERIPH_CLKSTAT10 + */ +#define PERI_CLK10_IPF_CCPU (1 << 0) +#define PERI_CLK10_SOCP_CCPU (1 << 1) +#define PERI_CLK10_SECENG_CCPU (1 << 2) +#define PERI_CLK10_HARQ_CCPU (1 << 3) +#define PERI_CLK10_IPF_MCU (1 << 16) +#define PERI_CLK10_SOCP_MCU (1 << 17) +#define PERI_CLK10_SECENG_MCU (1 << 18) +#define PERI_CLK10_HARQ_MCU (1 << 19) + +/* + * PERI_SC_PERIPH_CLKEN12 + * PERI_SC_PERIPH_CLKDIS12 + * PERI_SC_PERIPH_CLKSTAT12 + */ +#define PERI_CLK12_HIFI_SRC (1 << 0) +#define PERI_CLK12_MMC0_SRC (1 << 1) +#define PERI_CLK12_MMC1_SRC (1 << 2) +#define PERI_CLK12_MMC2_SRC (1 << 3) +#define PERI_CLK12_SYSPLL_DIV (1 << 4) +#define PERI_CLK12_TPIU_SRC (1 << 5) +#define PERI_CLK12_MMC0_HF (1 << 6) +#define PERI_CLK12_MMC1_HF (1 << 7) +#define PERI_CLK12_PLL_TEST_SRC (1 << 8) +#define PERI_CLK12_CODEC_SOC (1 << 9) +#define PERI_CLK12_MEDIA (1 << 10) + +/* + * PERI_SC_PERIPH_RSTEN0 + * PERI_SC_PERIPH_RSTDIS0 + * PERI_SC_PERIPH_RSTSTAT0 + */ +#define PERI_RST0_MMC0 (1 << 0) +#define PERI_RST0_MMC1 (1 << 1) +#define PERI_RST0_MMC2 (1 << 2) +#define PERI_RST0_NANDC (1 << 3) +#define PERI_RST0_USBOTG_BUS (1 << 4) +#define PERI_RST0_POR_PICOPHY (1 << 5) +#define PERI_RST0_USBOTG (1 << 6) +#define PERI_RST0_USBOTG_32K (1 << 7) + +/* + * PERI_SC_PERIPH_RSTEN1 + * PERI_SC_PERIPH_RSTDIS1 + * PERI_SC_PERIPH_RSTSTAT1 + */ +#define PERI_RST1_HIFI (1 << 0) +#define PERI_RST1_DIGACODEC (1 << 5) + +/* + * PERI_SC_PERIPH_RSTEN2 + * PERI_SC_PERIPH_RSTDIS2 + * PERI_SC_PERIPH_RSTSTAT2 + */ +#define PERI_RST2_IPF (1 << 0) +#define PERI_RST2_SOCP (1 << 1) +#define PERI_RST2_DMAC (1 << 2) +#define PERI_RST2_SECENG (1 << 3) +#define PERI_RST2_ABB (1 << 4) +#define PERI_RST2_HPM0 (1 << 5) +#define PERI_RST2_HPM1 (1 << 6) +#define PERI_RST2_HPM2 (1 << 7) +#define PERI_RST2_HPM3 (1 << 8) + +/* + * PERI_SC_PERIPH_RSTEN3 + * PERI_SC_PERIPH_RSTDIS3 + * PERI_SC_PERIPH_RSTSTAT3 + */ +#define PERI_RST3_CSSYS (1 << 0) +#define PERI_RST3_I2C0 (1 << 1) +#define PERI_RST3_I2C1 (1 << 2) +#define PERI_RST3_I2C2 (1 << 3) +#define PERI_RST3_I2C3 (1 << 4) +#define PERI_RST3_UART1 (1 << 5) +#define PERI_RST3_UART2 (1 << 6) +#define PERI_RST3_UART3 (1 << 7) +#define PERI_RST3_UART4 (1 << 8) +#define PERI_RST3_SSP (1 << 9) +#define PERI_RST3_PWM (1 << 10) +#define PERI_RST3_BLPWM (1 << 11) +#define PERI_RST3_TSENSOR (1 << 12) +#define PERI_RST3_DAPB (1 << 18) +#define PERI_RST3_HKADC (1 << 19) +#define PERI_RST3_CODEC (1 << 20) + +/* + * PERI_SC_PERIPH_RSTEN8 + * PERI_SC_PERIPH_RSTDIS8 + * PERI_SC_PERIPH_RSTSTAT8 + */ +#define PERI_RST8_RS0 (1 << 0) +#define PERI_RST8_RS2 (1 << 1) +#define PERI_RST8_RS3 (1 << 2) +#define PERI_RST8_MS0 (1 << 3) +#define PERI_RST8_MS2 (1 << 5) +#define PERI_RST8_XG2RAM0 (1 << 6) +#define PERI_RST8_X2SRAM_TZMA (1 << 7) +#define PERI_RST8_SRAM (1 << 8) +#define PERI_RST8_HARQ (1 << 10) +#define PERI_RST8_DDRC (1 << 12) +#define PERI_RST8_DDRC_APB (1 << 13) +#define PERI_RST8_DDRPACK_APB (1 << 14) +#define PERI_RST8_DDRT (1 << 17) + +#endif /* __HI6220_PERI_H__ */ diff --git a/plat/hikey/include/hi6220_regs_pmctrl.h b/plat/hikey/include/hi6220_regs_pmctrl.h new file mode 100644 index 0000000..4a2e905 --- /dev/null +++ b/plat/hikey/include/hi6220_regs_pmctrl.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. + * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __HI6220_REGS_PMCTRL_H__ +#define __HI6220_REGS_PMCTRL_H__ + +#define PMCTRL_BASE 0xF7032000 + +#define PMCTRL_ACPUPLLCTRL (PMCTRL_BASE + 0x000) +#define PMCTRL_ACPUPLLFREQ (PMCTRL_BASE + 0x004) +#define PMCTRL_DDRPLL1CTRL (PMCTRL_BASE + 0x010) +#define PMCTRL_DDRPLL0CTRL (PMCTRL_BASE + 0x030) +#define PMCTRL_MEDPLLCTRL (PMCTRL_BASE + 0x038) +#define PMCTRL_ACPUPLLSEL (PMCTRL_BASE + 0x100) +#define PMCTRL_ACPUCLKDIV (PMCTRL_BASE + 0x104) +#define PMCTRL_ACPUSYSPLLCFG (PMCTRL_BASE + 0x110) +#define PMCTRL_ACPUCLKOFFCFG (PMCTRL_BASE + 0x114) +#define PMCTRL_ACPUPLLFRAC (PMCTRL_BASE + 0x134) +#define PMCTRL_ACPUPMUVOLUPTIME (PMCTRL_BASE + 0x360) +#define PMCTRL_ACPUPMUVOLDNTIME (PMCTRL_BASE + 0x364) +#define PMCTRL_ACPUVOLPMUADDR (PMCTRL_BASE + 0x368) +#define PMCTRL_ACPUVOLUPSTEP (PMCTRL_BASE + 0x36c) +#define PMCTRL_ACPUVOLDNSTEP (PMCTRL_BASE + 0x370) +#define PMCTRL_ACPUDFTVOL (PMCTRL_BASE + 0x374) +#define PMCTRL_ACPUDESTVOL (PMCTRL_BASE + 0x378) +#define PMCTRL_ACPUVOLTTIMEOUT (PMCTRL_BASE + 0x37c) + +#define PMCTRL_ACPUPLLCTRL_EN_CFG (1 << 0) + +#define PMCTRL_ACPUCLKDIV_CPUEXT_CFG_MASK (3 << 0) +#define PMCTRL_ACPUCLKDIV_DDR_CFG_MASK (3 << 8) +#define PMCTRL_ACPUCLKDIV_CPUEXT_STAT_MASK (3 << 16) +#define PMCTRL_ACPUCLKDIV_DDR_STAT_MASK (3 << 24) + +#define PMCTRL_ACPUPLLSEL_ACPUPLL_CFG (1 << 0) +#define PMCTRL_ACPUPLLSEL_ACPUPLL_STAT (1 << 1) +#define PMCTRL_ACPUPLLSEL_SYSPLL_STAT (1 << 2) + +#define PMCTRL_ACPUSYSPLL_CLKDIV_CFG_MASK 0x7 +#define PMCTRL_ACPUSYSPLL_CLKEN_CFG (1 << 4) +#define PMCTRL_ACPUSYSPLL_CLKDIV_SW (3 << 12) + +#define PMCTRL_ACPUSYSPLLCFG_SYSPLL_CLKEN (1 << 4) +#define PMCTRL_ACPUSYSPLLCFG_CLKDIV_MASK (3 << 12) + +#define PMCTRL_ACPUDESTVOL_DEST_VOL_MASK 0x7f +#define PMCTRL_ACPUDESTVOL_CURR_VOL_MASK (0x7f << 8) + +#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_START (0) +#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_END (0) +#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_rst_START (2) +#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_rst_END (2) +#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_time_START (4) +#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_time_END (27) +#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_START (28) +#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_END (28) +#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_lock_START (29) +#define SOC_PMCTRL_ACPUPLLCTRL_acpupll_lock_END (29) + +#define SOC_PMCTRL_ACPUPLLFRAC_ADDR(base) ((base) + (0x134)) +#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_sw_START (12) + +#define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_START (0) +#define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_END (0) +#define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_START (1) +#define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_END (1) +#define SOC_PMCTRL_ACPUPLLSEL_syspll_sw_stat_START (2) +#define SOC_PMCTRL_ACPUPLLSEL_syspll_sw_stat_END (2) + +#define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_START (0) +#define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_END (1) +#define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_START (8) +#define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_END (9) +#define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_START (16) +#define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_END (17) +#define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_START (24) +#define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_END (25) + +#define SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_START (0) +#define SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_END (6) +#define SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_START (8) +#define SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_END (14) + +#define SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_START (0) +#define SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_END (0) + +#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_cfg_START (0) +#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_cfg_END (2) +#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_START (4) +#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_END (4) +#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_cfg_START (8) +#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_cfg_END (9) +#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_stat_START (16) +#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_stat_END (19) +#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_stat_START (20) +#define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_stat_END (20) + +#endif /* __HI6220_REGS_PMCTRL_H__ */ diff --git a/plat/hikey/include/hi6553.h b/plat/hikey/include/hi6553.h index 0ce9eb8..aa5bfe1 100644 --- a/plat/hikey/include/hi6553.h +++ b/plat/hikey/include/hi6553.h @@ -40,6 +40,7 @@ #define DISABLE6_XO_CLK_RF1 (1 << 3) #define DISABLE6_XO_CLK_RF2 (1 << 4)
+#define VERSION_REG 0x000 #define PERI_EN_MARK 0x040 #define BUCK2_REG1 0x04a #define BUCK2_REG5 0x04e @@ -81,6 +82,9 @@ #define LED_GREEN_ENABLE (1 << 1) #define LED_OUT_CTRL 0x00
+#define PMU_HI6552_V300 0x30 +#define PMU_HI6552_V310 0x31 + extern unsigned char hi6553_read_8(unsigned int offset); extern void hi6553_write_8(unsigned int offset, unsigned int value);
diff --git a/plat/hikey/usb.c b/plat/hikey/usb.c index 40bd336..7415550 100644 --- a/plat/hikey/usb.c +++ b/plat/hikey/usb.c @@ -1106,20 +1106,20 @@ static void dvc_and_picophy_init_chip(void) unsigned int data;
/* enable USB clock */ - mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK_USBOTG); + mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_USBOTG); do { data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); - } while ((data & PERI_CLK_USBOTG) == 0); + } while ((data & PERI_CLK0_USBOTG) == 0);
/* out of reset */ mmio_write_32(PERI_SC_PERIPH_RSTDIS0, - PERI_RST_USBOTG_BUS | PERI_RST_PICOPHY | - PERI_RST_USBOTG | PERI_RST_USBOTG_32K); + PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY | + PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K); do { data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); - data &= PERI_RST_USBOTG_BUS | PERI_RST_PICOPHY | - PERI_RST_USBOTG | PERI_RST_USBOTG_32K; + data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY | + PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K; } while (data);
mmio_write_32(PERI_SC_PERIPH_CTRL8, EYE_PATTERN); @@ -1127,18 +1127,18 @@ static void dvc_and_picophy_init_chip(void) /* configure USB PHY */ data = mmio_read_32(PERI_SC_PERIPH_CTRL4); /* make PHY out of low power mode */ - data &= ~PERIPH_CTRL4_PICO_SIDDQ; + data &= ~PERI_CTRL4_PICO_SIDDQ; /* detect VBUS by external circuit, switch D+ to 1.5KOhm pullup */ - data |= PERIPH_CTRL4_PICO_VBUSVLDEXTSEL | PERIPH_CTRL4_PICO_VBUSVLDEXT; - data &= ~PERIPH_CTRL4_FPGA_EXT_PHY_SEL; + data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT; + data &= ~PERI_CTRL4_FPGA_EXT_PHY_SEL; /* select PHY */ - data &= ~PERIPH_CTRL4_OTG_PHY_SEL; + data &= ~PERI_CTRL4_OTG_PHY_SEL; mmio_write_32(PERI_SC_PERIPH_CTRL4, data);
udelay(1000);
data = mmio_read_32(PERI_SC_PERIPH_CTRL5); - data &= ~PERIPH_CTRL5_PICOPHY_BC_MODE; + data &= ~PERI_CTRL5_PICOPHY_BC_MODE; mmio_write_32(PERI_SC_PERIPH_CTRL5, data);
udelay(20000);
Add mcu image loading driver.
Signed-off-by: Leo Yan leo.yan@linaro.org --- plat/hikey/drivers/hisi_mcu.c | 247 ++++++++++++++++++++++++++++++++++++++++++ plat/hikey/include/hisi_mcu.h | 41 +++++++ 2 files changed, 288 insertions(+) create mode 100644 plat/hikey/drivers/hisi_mcu.c create mode 100644 plat/hikey/include/hisi_mcu.h
diff --git a/plat/hikey/drivers/hisi_mcu.c b/plat/hikey/drivers/hisi_mcu.c new file mode 100644 index 0000000..ac71f4c --- /dev/null +++ b/plat/hikey/drivers/hisi_mcu.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. + * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch_helpers.h> +#include <assert.h> +#include <bl_common.h> +#include <console.h> +#include <debug.h> +#include <partitions.h> +#include <platform.h> +#include <platform_def.h> +#include <string.h> +#include <mmio.h> +#include <hi6220.h> + +#define MCU_SECTION_MAX 30 + +enum MCU_IMAGE_SEC_TYPE_ENUM { + MCU_IMAGE_SEC_TYPE_TEXT = 0, /* text section */ + MCU_IMAGE_SEC_TYPE_DATA, /* data section */ + MCU_IMAGE_SEC_TYPE_BUTT +}; + +enum MCU_IMAGE_SEC_LOAD_ENUM { + MCU_IMAGE_SEC_LOAD_STATIC = 0, + MCU_IMAGE_SEC_LOAD_DYNAMIC, + MCU_IMAGE_SEC_LOAD_BUFFER, + MCU_IMAGE_SEC_LOAD_MODEM_ENTRY, + MCU_IMAGE_SEC_LOAD_BUTT +}; + +struct mcu_image_sec { + unsigned short serial; + char type; + char load_attr; + uint32_t src_offset; /* offset in image */ + uint32_t dst_offset; /* offset in memory */ + uint32_t size; +}; + +struct mcu_image_head { + char time_stamp[24]; + uint32_t image_size; + uint32_t secs_num; + struct mcu_image_sec secs[MCU_SECTION_MAX]; +}; + +#define SOC_SRAM_M3_BASE_ADDR (0xF6000000) + +#define MCU_SRAM_SIZE (0x0000C000) +#define MCU_CACHE_SIZE (0x00004000) +#define MCU_CODE_SIZE (MCU_SRAM_SIZE - MCU_CACHE_SIZE) + +#define MCU_SYS_MEM_ADDR (0x05E00000) +#define MCU_SYS_MEM_SIZE (0x00100000) + +#if 0 +static uint32_t ap2mcu_addr(uint32_t ap_addr) +{ + if (ap_addr >= SOC_SRAM_M3_BASE_ADDR && + ap_addr < SOC_SRAM_M3_BASE_ADDR + MCU_SRAM_SIZE) + return ap_addr - SOC_SRAM_M3_BASE_ADDR; + else if (ap_addr >= MCU_SYS_MEM_ADDR && + ap_addr < MCU_SYS_MEM_ADDR + MCU_SYS_MEM_SIZE ) + return ap_addr - MCU_SYS_MEM_ADDR + MCU_SRAM_SIZE; + else + return ap_addr; +} +#endif + +static uint32_t mcu2ap_addr(uint32_t mcu_addr) +{ + if (mcu_addr < MCU_CODE_SIZE) + return (mcu_addr + SOC_SRAM_M3_BASE_ADDR); + else if ((mcu_addr >= MCU_SRAM_SIZE) && + (mcu_addr < MCU_SRAM_SIZE + MCU_SYS_MEM_SIZE)) + return mcu_addr - MCU_SRAM_SIZE + MCU_SYS_MEM_ADDR; + else + return mcu_addr; +} + +static int is_binary_header_invalid(struct mcu_image_head *head, + unsigned length) +{ + /* invalid cases */ + if ((head->image_size == 0) || + (head->image_size > length) || + (head->secs_num > MCU_SECTION_MAX) || + (head->secs_num == 0)) + return 1; + + return 0; +} + +static int is_binary_section_invalid(struct mcu_image_sec *sec, + struct mcu_image_head *head) +{ + unsigned long ap_dst_offset = 0; + + if ((sec->serial >= head->secs_num) || + (sec->src_offset + sec->size > head->image_size)) + return 1; + + if ((sec->type >= MCU_IMAGE_SEC_TYPE_BUTT) || + (sec->load_attr >= MCU_IMAGE_SEC_LOAD_BUTT)) + return 1; + + ap_dst_offset = mcu2ap_addr(sec->dst_offset); + if ((ap_dst_offset >= SOC_SRAM_M3_BASE_ADDR) && + (ap_dst_offset < SOC_SRAM_M3_BASE_ADDR + 0x20000 - sec->size)) + return 0; + else if ((ap_dst_offset >= MCU_SYS_MEM_ADDR) && + (ap_dst_offset < MCU_SYS_MEM_ADDR + MCU_SYS_MEM_SIZE - sec->size)) + return 0; + else if ((ap_dst_offset >= 0xfff8e000) && + (ap_dst_offset < 0xfff91c00 - sec->size)) + return 0; + + ERROR("%s: mcu destination address invalid.\n", __func__); + ERROR("%s: number=%d, dst offset=%d size=%d\n", + __func__, sec->serial, sec->dst_offset, sec->size); + return 1; +} + +void hisi_mcu_enable_sram(void) +{ + mmio_write_32(AO_SC_PERIPH_CLKEN4, + AO_SC_PERIPH_CLKEN4_HCLK_IPC_S | + AO_SC_PERIPH_CLKEN4_HCLK_IPC_NS); + + /* set register to enable dvfs which is used by mcu */ + mmio_write_32(PERI_SC_RESERVED8_ADDR, 0x02000020); + + /* mcu mem is powered on, need de-assert reset */ + mmio_write_32(AO_SC_PERIPH_RSTDIS4, + AO_SC_PERIPH_RSTDIS4_RESET_MCU_ECTR_N); + + /* enable mcu hclk */ + mmio_write_32(AO_SC_PERIPH_CLKEN4, + AO_SC_PERIPH_CLKEN4_HCLK_MCU | + AO_SC_PERIPH_CLKEN4_CLK_MCU_DAP); +} + +void hisi_mcu_start_run(void) +{ + unsigned int val; + +#if 0 + /* set mcu's self loop instruction 0xE7FE at entry point */ + val = mmio_read_32((SOC_SRAM_M3_BASE_ADDR + 0x200)); + val &= 0xFFFF0000; + val |= 0xE7FE; + mmio_write_32((SOC_SRAM_M3_BASE_ADDR + 0x200), val); +#endif + + /* set mcu ddr remap configuration */ + mmio_write_32(AO_SC_MCU_SUBSYS_CTRL2, MCU_SYS_MEM_ADDR); + + /* de-assert reset for mcu and to run */ + mmio_write_32(AO_SC_PERIPH_RSTDIS4, + AO_SC_PERIPH_RSTDIS4_RESET_MCU_ECTR_N | + AO_SC_PERIPH_RSTDIS4_RESET_MCU_SYS_N | + AO_SC_PERIPH_RSTDIS4_RESET_MCU_POR_N | + AO_SC_PERIPH_RSTDIS4_RESET_MCU_DAP_N); + + val = mmio_read_32(AO_SC_SYS_CTRL2); + mmio_write_32(AO_SC_SYS_CTRL2, + val | AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR); + + INFO("%s: AO_SC_SYS_CTRL2=%x\n", __func__, + mmio_read_32(AO_SC_SYS_CTRL2)); +} + +int hisi_mcu_load_image(uintptr_t image_base, uint32_t image_size) +{ + unsigned int i; + struct mcu_image_head *head; + char *buf; + + head = (struct mcu_image_head *)image_base; + if (is_binary_header_invalid(head, image_size)) { + ERROR("Invalid %s image header.\n", head->time_stamp); + return -1; + } + + buf = (char *)head; + for (i = 0; i < head->secs_num; i++) { + + int *src, *dst; + + /* check the sections */ + if (is_binary_section_invalid(&head->secs[i], head)) { + ERROR("Invalid mcu section.\n"); + return -1; + } + + /* check if the section is static-loaded */ + if (head->secs[i].load_attr != MCU_IMAGE_SEC_LOAD_STATIC) + continue; + + /* copy the sections */ + src = (int *)(intptr_t)(buf + head->secs[i].src_offset); + dst = (int *)(intptr_t)mcu2ap_addr(head->secs[i].dst_offset); + + memcpy((void *)dst, (void *)src, head->secs[i].size); + + INFO("%s: mcu sections %d:\n", __func__, i); + INFO("%s: src = 0x%x\n", __func__, src); + INFO("%s: dst = 0x%x\n", __func__, dst); + INFO("%s: size = %d\n", __func__, head->secs[i].size); + + INFO("%s: [SRC 0x%x] 0x%x 0x%x 0x%x 0x%x\n", __func__, + src, src[0], src[1], src[2], src[3]); + INFO("%s: [DST 0x%x] 0x%x 0x%x 0x%x 0x%x\n", __func__, + dst, dst[0], dst[1], dst[2], dst[3]); + } + + return 0; +} diff --git a/plat/hikey/include/hisi_mcu.h b/plat/hikey/include/hisi_mcu.h new file mode 100644 index 0000000..74dbf17 --- /dev/null +++ b/plat/hikey/include/hisi_mcu.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. + * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MCU_H__ +#define __MCU_H__ + +#include <stdint.h> + +extern void hisi_mcu_enable_sram(void); +extern void hisi_mcu_start_run(void); +extern int hisi_mcu_load_image(uintptr_t image_base, uint32_t image_size); + +#endif /* __MCU_H__ */
Signed-off-by: Leo Yan leo.yan@linaro.org --- plat/hikey/drivers/hisi_adc.c | 218 ++++++++++++++++++++++++++++++++++++++++ plat/hikey/include/hisi_hkadc.h | 152 ++++++++++++++++++++++++++++ 2 files changed, 370 insertions(+) create mode 100644 plat/hikey/drivers/hisi_adc.c create mode 100644 plat/hikey/include/hisi_hkadc.h
diff --git a/plat/hikey/drivers/hisi_adc.c b/plat/hikey/drivers/hisi_adc.c new file mode 100644 index 0000000..1d9527a --- /dev/null +++ b/plat/hikey/drivers/hisi_adc.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. + * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch_helpers.h> +#include <assert.h> +#include <bl_common.h> +#include <console.h> +#include <debug.h> +#include <hi6220.h> +#include <mmio.h> +#include <partitions.h> +#include <platform.h> +#include <platform_def.h> +#include <sp804_timer.h> +#include <string.h> + +void init_hkadc(void) +{ + /* reset hkadc */ + mmio_write_32(PERI_SC_PERIPH_RSTEN3, PERI_RST3_HKADC); + udelay(2); + mmio_write_32(PERI_SC_PERIPH_RSTDIS3, PERI_RST3_HKADC); + udelay(2); + + /* enable clock */ + mmio_write_32(PERI_SC_PERIPH_CLKDIS3, PERI_CLK3_HKADC); + udelay(2); + mmio_write_32(PERI_SC_PERIPH_CLKEN3, PERI_CLK3_HKADC); + udelay(2); + + return; +} + +int hkadc_bbp_convert(unsigned char enchan, int *pusvalue) +{ + unsigned int val = 0x00; + unsigned int count = 0x0; + unsigned short ret = 0; + unsigned short rd_data0 = 0; + unsigned short rd_data1 = 0; + + /* set channel, rate and eanble pmu hkadc */ + val = HKADC_WR01_VALUE | enchan; + + /* config operation */ + mmio_write_32(HKADC_WR01_DATA, val); + mmio_write_32(HKADC_WR23_DATA, HKADC_WR23_VALUE); + mmio_write_32(HKADC_WR45_DATA, HKADC_WR45_VALUE); + + /* set operation number*/ + mmio_write_32(HKADC_WR_NUM, HKADC_WR_NUM_VALUE); + + /* set delay for operations */ + mmio_write_32(HKADC_DELAY01, HKADC_DELAY01_VALUE); + mmio_write_32(HKADC_DELAY23, HKADC_DELAY23_VALUE); + + /* enable hkadc */ + mmio_write_32(HKADC_DSP_START, 0x1); + + /* check if the enable bit has been cleared */ + do { + if (count > HKADC_START_TIMEOUT) { + /* disable hkadc and return error */ + mmio_write_32(HKADC_DSP_START, 0x0); + ERROR("%s: HKADC start failed! (%d)\n", __func__); + return -1; + } + + val = mmio_read_32(HKADC_DSP_START); + count++; + } while(val & 0x1); + + /* read back adc result */ + rd_data0 = mmio_read_32(HKADC_DSP_RD2_DATA); + rd_data1 = mmio_read_32(HKADC_DSP_RD3_DATA); + + /* combine result */ + ret = (((rd_data1 << 4) & HKADC_VALUE_HIGH) | + ((rd_data0 >> 4) & HKADC_VALUE_LOW)); + + *pusvalue = (ret & HKADC_VALID_VALUE) * HKADC_VREF_1V8; + *pusvalue = *pusvalue >> 12; + + INFO("[BDID] bbp convert: data=%d, count=%d, value=%d\n", + ret, count, *pusvalue ); + return 0; +} + +/* + * Convert adcin raw data (12-bit) to remapping data (4-bit). + */ +int hkadc_adcin_data_remap(int adcin_value) +{ + unsigned int ret = BOARDID_UNKNOW; + + if (adcin_value < 0) + ret = BOARDID_UNKNOW; + else if (adcin_value <= BOUNDARY_VALUE0) + ret = BOARDID_VALUE0; + else if (adcin_value <= BOUNDARY_VALUE1) + ret = BOARDID_VALUE1; + else if (adcin_value <= BOUNDARY_VALUE2) + ret = BOARDID_VALUE2; + else if (adcin_value <= BOUNDARY_VALUE3) + ret = BOARDID_VALUE3; + else if (adcin_value <= BOUNDARY_VALUE4) + ret = BOARDID_VALUE4; + else if (adcin_value <= BOUNDARY_VALUE5) + ret = BOARDID_VALUE5; + else if (adcin_value <= BOUNDARY_VALUE6) + ret = BOARDID_VALUE6; + else if (adcin_value <= BOUNDARY_VALUE7) + ret = BOARDID_VALUE7; + else if (adcin_value <= BOUNDARY_VALUE8) + ret = BOARDID_VALUE8; + else if (adcin_value <= BOUNDARY_VALUE9) + ret = BOARDID_VALUE9; + else + ret = BOARDID_UNKNOW; + + return ret; +} + +int hkadc_read_board_id(unsigned int *data) +{ + int adcin0, adcin1, adcin2; + int ret; + + /* read adc channel data */ + ret = hkadc_bbp_convert(HKADC_CHAN_BOARDID0, &adcin0); + if (ret == -1) { + ERROR("[BDID] failed read board id chan=%d, adc=%d\n", + HKADC_CHAN_BOARDID0, adcin0); + return ret; + } + INFO("[BDID] adcin0_V:%d\n", adcin0); + + adcin0 = hkadc_adcin_data_remap(adcin0); + INFO("[BDID] adcin0_remap:0x%x\n", adcin0); + + ret = hkadc_bbp_convert(HKADC_CHAN_BOARDID1, &adcin1); + if (ret == -1) { + ERROR("[BDID] failed read board id chan=%d, adc=%d\n", + HKADC_CHAN_BOARDID1, adcin1); + return ret; + } + INFO("[BDID] adcin1_V:%d\n", adcin1); + + adcin1 = hkadc_adcin_data_remap(adcin1); + INFO("[BDID] adcin1_remap:0x%x\n", adcin1); + + ret = hkadc_bbp_convert(HKADC_CHAN_BOARDID2, &adcin2); + if (ret == -1) { + ERROR("[BDID] failed read board id chan=%d, adc=%d\n", + HKADC_CHAN_BOARDID2, adcin2); + return ret; + } + INFO("[BDID] adcin2_V:%d\n", adcin2); + + adcin2 = hkadc_adcin_data_remap(adcin2); + INFO("[BDID] adcin2_remap:0x%x\n", adcin2); + + /* Composed to adcin data to decimal boardid */ + *data = adcin2 * 100 + adcin1 * 10 + adcin0; + INFO("[BDID] boardid: %d %d %d %d\n", *data, adcin2, adcin1, adcin0); + + return 0; +} + +void init_boardid(void) +{ + unsigned int actual_boardid; + unsigned int reg; + + hkadc_read_board_id(&actual_boardid); + + /* Set chip id to sram */ + reg = read_midr_el1(); + mmio_write_32(MEMORY_AXI_CHIP_ADDR, reg); + INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR, reg); + + /* Set board type to sram */ + mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0x0); + INFO("[BDID] [%x] board type: 0\n", MEMORY_AXI_BOARD_TYPE_ADDR); + + /* Set board id to sram */ + mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b); + INFO("[BDID] [%x] board id: 0x2b\n", MEMORY_AXI_BOARD_ID_ADDR); + return; +} diff --git a/plat/hikey/include/hisi_hkadc.h b/plat/hikey/include/hisi_hkadc.h new file mode 100644 index 0000000..e0189d3 --- /dev/null +++ b/plat/hikey/include/hisi_hkadc.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. + * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __HISI_HKADC_H__ +#define __HISI_HKADC_H__ + +/* hkadc channel */ +#define HKADC_CHAN_UNUSE0 (0x00) +#define HKADC_CHAN_BOARDID1 (0x01) +#define HKADC_CHAN_BOARDID2 (0x02) +#define HKADC_CHAN_BOARDID0 (0x04) +#define HKADC_CHAN_VCOINMON (0x06) +#define HKADC_CHAN_RTMP (0x0A) +#define HKADC_CHAN_VBATMON (0x0B) + +/* hkadc registers */ +#define HKADC_BASE (0xF7013000) + +#define HKADC_DSP_START (HKADC_BASE + 0x0000) +#define HKADC_DSP_CFG (HKADC_BASE + 0x0004) +#define HKADC_WR_NUM (HKADC_BASE + 0x0008) +#define HKADC_DSP_WAIT_TIME (HKADC_BASE + 0x000C) +#define HKADC_TIMEOUT_ERR_CLR (HKADC_BASE + 0x0010) +#define HKADC_TIMEOUT_ERR (HKADC_BASE + 0x0018) +#define HKADC_DSP_START_CLR (HKADC_BASE + 0x001C) +#define HKADC_WR01_DATA (HKADC_BASE + 0x0020) +#define HKADC_WR23_DATA (HKADC_BASE + 0x0024) +#define HKADC_WR45_DATA (HKADC_BASE + 0x0028) +#define HKADC_WR67_DATA (HKADC_BASE + 0x002C) +#define HKADC_DELAY01 (HKADC_BASE + 0x0030) +#define HKADC_DELAY23 (HKADC_BASE + 0x0034) +#define HKADC_DELAY45 (HKADC_BASE + 0x0038) +#define HKADC_DELAY6 (HKADC_BASE + 0x003C) +#define HKADC_DSP_RD0_DATA (HKADC_BASE + 0x0040) +#define HKADC_DSP_RD1_DATA (HKADC_BASE + 0x0044) +#define HKADC_DSP_RD2_DATA (HKADC_BASE + 0x0048) +#define HKADC_DSP_RD3_DATA (HKADC_BASE + 0x004C) +#define HKADC_DSP_RD4_DATA (HKADC_BASE + 0x0050) +#define HKADC_DSP_RD5_DATA (HKADC_BASE + 0x0054) +#define HKADC_DSP_RD6_DATA (HKADC_BASE + 0x0058) +#define HKADC_DSP_RD7_DATA (HKADC_BASE + 0x005C) +#define HKADC_OP_INTERVAL (HKADC_BASE + 0x0060) +#define HKADC_OP_INTERVAL_BYPASS (HKADC_BASE + 0x0064) +#define HKADC_CHANNEL_EN (HKADC_BASE + 0x0068) +#define HKADC_DBG_INFO (HKADC_BASE + 0x00D0) +#define HKADC_FINSH_RAW_INT (HKADC_BASE + 0x0100) +#define HKADC_FINSH_MSK_INT (HKADC_BASE + 0x0104) +#define HKADC_FINSH_INT_CLR (HKADC_BASE + 0x0108) +#define HKADC_FINSH_INT_MSK (HKADC_BASE + 0x010C) + +#define PMU_HKADC_CFG_ADDR (0x00) +#define PMU_HKADC_START_ADDR (0x01) +#define PMU_HKADC_STATUS_ADDR (0x02) +#define PMU_HKADC_RDHIGH_ADDR (0x03) +#define PMU_HKADC_RDLOW_ADDR (0x04) + +#define HKADC_WR01_VALUE \ + ((0x0 << 31) | \ + (PMU_HKADC_START_ADDR << 24) | \ + (0x1 << 16) | \ + (0x0 << 15) | \ + (PMU_HKADC_CFG_ADDR << 8) | \ + (0x3 << 5)) + +#define HKADC_WR23_VALUE \ + ((0x1 << 31) | \ + (PMU_HKADC_RDHIGH_ADDR << 24) | \ + (0x1 << 15) | \ + (PMU_HKADC_RDLOW_ADDR << 8)) + +#define HKADC_WR45_VALUE \ + ((0x0 << 15) | \ + (PMU_HKADC_CFG_ADDR << 8) | \ + (0x80 << 0)) + +#define HKADC_WR_NUM_VALUE (5) +#define HKADC_DELAY01_VALUE ((0x0700 << 16) | (0x0200 << 0)) +#define HKADC_DELAY23_VALUE ((0x00c8 << 16) | (0x00c8 << 0)) +#define HKADC_START_TIMEOUT (2000) + +#define HKADC_VALUE_HIGH (0x0FF0) +#define HKADC_VALUE_LOW (0x000F) +#define HKADC_VALID_VALUE (0x0FFF) +#define HKADC_VREF_1V8 1800 + +#define HKADC_DATA_VOLT_GRADE0 (0) +#define HKADC_DATA_VOLT_GRADE1 (100) +#define HKADC_DATA_VOLT_GRADE2 (300) +#define HKADC_DATA_VOLT_GRADE3 (500) +#define HKADC_DATA_VOLT_GRADE4 (700) +#define HKADC_DATA_VOLT_GRADE5 (900) +#define HKADC_DATA_VOLT_GRADE6 (1100) +#define HKADC_DATA_VOLT_GRADE7 (1300) +#define HKADC_DATA_VOLT_GRADE8 (1500) +#define HKADC_DATA_VOLT_GRADE9 (1700) +#define HKADC_DATA_VOLT_GRADE10 (1800) + +#define BOUNDARY_VALUE0 HKADC_DATA_VOLT_GRADE1 +#define BOUNDARY_VALUE1 HKADC_DATA_VOLT_GRADE2 +#define BOUNDARY_VALUE2 HKADC_DATA_VOLT_GRADE3 +#define BOUNDARY_VALUE3 HKADC_DATA_VOLT_GRADE4 +#define BOUNDARY_VALUE4 HKADC_DATA_VOLT_GRADE5 +#define BOUNDARY_VALUE5 HKADC_DATA_VOLT_GRADE6 +#define BOUNDARY_VALUE6 HKADC_DATA_VOLT_GRADE7 +#define BOUNDARY_VALUE7 HKADC_DATA_VOLT_GRADE8 +#define BOUNDARY_VALUE8 HKADC_DATA_VOLT_GRADE9 +#define BOUNDARY_VALUE9 HKADC_DATA_VOLT_GRADE10 + +#define BOARDID_VALUE0 (0x0) +#define BOARDID_VALUE1 (0x1) +#define BOARDID_VALUE2 (0x2) +#define BOARDID_VALUE3 (0x3) +#define BOARDID_VALUE4 (0x4) +#define BOARDID_VALUE5 (0x5) +#define BOARDID_VALUE6 (0x6) +#define BOARDID_VALUE7 (0x7) +#define BOARDID_VALUE8 (0x8) +#define BOARDID_VALUE9 (0x9) +#define BOARDID_UNKNOW (0xF) + +extern void init_hkadc(void); +extern void init_boardid(void); + +#endif /* __HISI_HKADC_H__ */
The sram has been divided into several parts, and every part has dedicated usage for power management, TEE OS, etc. So use this file to define the layout for sram.
Signed-off-by: Leo Yan leo.yan@linaro.org --- plat/hikey/include/hisi_sram_map.h | 307 +++++++++++++++++++++++++++++++++++++ 1 file changed, 307 insertions(+) create mode 100644 plat/hikey/include/hisi_sram_map.h
diff --git a/plat/hikey/include/hisi_sram_map.h b/plat/hikey/include/hisi_sram_map.h new file mode 100644 index 0000000..90fa036 --- /dev/null +++ b/plat/hikey/include/hisi_sram_map.h @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. + * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SRAM_MAP_H__ +#define __SRAM_MAP_H__ + +/* + * SRAM Memory Region Layout + * + * +-----------------------+ + * | Low Power Mode | 7KB + * +-----------------------+ + * | Secure OS | 64KB + * +-----------------------+ + * | Software Flag | 1KB + * +-----------------------+ + * + */ + +#define SOC_SRAM_OFF_BASE_ADDR (0xFFF80000) + +/* PM Section: 7KB */ +#define SRAM_PM_ADDR (SOC_SRAM_OFF_BASE_ADDR) +#define SRAM_PM_SIZE (0x00001C00) + +/* TEE OS Section: 64KB */ +#define SRAM_TEEOS_ADDR (SRAM_PM_ADDR + SRAM_PM_SIZE) +#define SRAM_TEEOS_SIZE (0x00010000) + +/* General Use Section: 1KB */ +#define SRAM_GENERAL_ADDR (SRAM_TEEOS_ADDR + SRAM_TEEOS_SIZE) +#define SRAM_GENERAL_SIZE (0x00000400) + +/* + * General Usage Section Layout: + * + * +-----------------------+ + * | AP boot flag | 64B + * +-----------------------+ + * | DICC flag | 32B + * +-----------------------+ + * | Soft flag | 256B + * +-----------------------+ + * | Thermal flag | 128B + * +-----------------------+ + * | CSHELL | 4B + * +-----------------------+ + * | Uart Switching | 4B + * +-----------------------+ + * | ICC | 1024B + * +-----------------------+ + * | Memory Management | 1024B + * +-----------------------+ + * | IFC | 32B + * +-----------------------+ + * | HIFI | 32B + * +-----------------------+ + * | DDR capacity | 4B + * +-----------------------+ + * | Reserved | + * +-----------------------+ + * + */ + +/* App Core Boot Flags */ +#define MEMORY_AXI_ACPU_START_ADDR (SRAM_GENERAL_ADDR) +#define MEMORY_AXI_ACPU_START_SIZE (64) + +#define MEMORY_AXI_SRESET_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0000) +#define MEMORY_AXI_SECOND_CPU_BOOT_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0004) +#define MEMORY_AXI_READY_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0008) +#define MEMORY_AXI_FASTBOOT_ENTRY_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x000C) +#define MEMORY_AXI_PD_CHARGE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0010) +#define MEMORY_AXI_DBG_ALARM_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0014) +#define MEMORY_AXI_CHIP_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0018) +#define MEMORY_AXI_BOARD_TYPE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x001C) +#define MEMORY_AXI_BOARD_ID_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0020) +#define MEMORY_AXI_CHARGETYPE_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0024) +#define MEMORY_AXI_COLD_START_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0028) +#define MEMORY_AXI_ANDROID_REBOOT_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x002C) +#define MEMORY_AXI_ACPU_WDTRST_REBOOT_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0030) +#define MEMORY_AXI_ABNRST_BITMAP_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0034) +#define MEMORY_AXI_32K_CLK_TYPE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0038) +#define AXI_MODEM_PANIC_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x003C) +#define AXI_MODEM_PANIC_FLAG (0x68697369) +#define MEMORY_AXI_ACPU_END_ADDR (AXI_MODEM_PANIC_FLAG_ADDR + 4) + +/* DICC Flags */ +#define MEMORY_AXI_DICC_ADDR (MEMORY_AXI_ACPU_START_ADDR + MEMORY_AXI_ACPU_START_SIZE) +#define MEMORY_AXI_DICC_SIZE (32) + +#define MEMORY_AXI_SOFT_FLAG_ADDR (MEMORY_AXI_DICC_ADDR + MEMORY_AXI_DICC_SIZE) +#define MEMORY_AXI_SOFT_FLAG_SIZE (256) + +/* Thermal Flags */ +#define MEMORY_AXI_TEMP_PROTECT_ADDR (MEMORY_AXI_SOFT_FLAG_ADDR + MEMORY_AXI_SOFT_FLAG_SIZE) +#define MEMORY_AXI_TEMP_PROTECT_SIZE (128) + +/* CSHELL */ +#define MEMORY_AXI_USB_CSHELL_ADDR (MEMORY_AXI_TEMP_PROTECT_ADDR + MEMORY_AXI_TEMP_PROTECT_SIZE) +#define MEMORY_AXI_USB_CSHELL_SIZE (4) + +/* Uart and A/C Shell Switch Flags */ +#define MEMORY_AXI_UART_INOUT_ADDR (MEMORY_AXI_USB_CSHELL_ADDR + MEMORY_AXI_USB_CSHELL_SIZE) +#define MEMORY_AXI_UART_INOUT_SIZE (4) + +/* IFC Flags */ +#define MEMORY_AXI_IFC_ADDR (MEMORY_AXI_UART_INOUT_ADDR + MEMORY_AXI_UART_INOUT_SIZE) +#define MEMORY_AXI_IFC_SIZE (32) + +/* HIFI Data */ +#define MEMORY_AXI_HIFI_ADDR (MEMORY_AXI_IFC_ADDR + MEMORY_AXI_IFC_SIZE) +#define MEMORY_AXI_HIFI_SIZE (32) + +/* CONFIG Flags */ +#define MEMORY_AXI_CONFIG_ADDR (MEMORY_AXI_HIFI_ADDR + MEMORY_AXI_HIFI_SIZE) +#define MEMORY_AXI_CONFIG_SIZE (32) + +/* DDR Capacity Flags */ +#define MEMORY_AXI_DDR_CAPACITY_ADDR (MEMORY_AXI_CONFIG_ADDR + MEMORY_AXI_CONFIG_SIZE) +#define MEMORY_AXI_DDR_CAPACITY_SIZE (4) + +/* USB Shell Flags */ +#define MEMORY_AXI_USB_SHELL_FLAG_ADDR (MEMORY_AXI_DDR_CAPACITY_ADDR + MEMORY_AXI_DDR_CAPACITY_SIZE ) +#define MEMORY_AXI_USB_SHELL_FLAG_SIZE (4) + +/* MCU WDT Switch Flag */ +#define MEMORY_AXI_MCU_WDT_FLAG_ADDR (MEMORY_AXI_USB_SHELL_FLAG_ADDR + MEMORY_AXI_USB_SHELL_FLAG_SIZE) +#define MEMORY_AXI_MCU_WDT_FLAG_SIZE (4) + +/* TLDSP Mailbox MNTN */ +#define SRAM_DSP_MNTN_INFO_ADDR (MEMORY_AXI_MCU_WDT_FLAG_ADDR + MEMORY_AXI_MCU_WDT_FLAG_SIZE) +#define SRAM_DSP_MNTN_SIZE (32) + +/* TLDSP ARM Mailbox Protect Flag */ +#define SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_ADDR (SRAM_DSP_MNTN_INFO_ADDR + SRAM_DSP_MNTN_SIZE) +#define SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_SIZE (4) + +/* RTT Sleep Flag */ +#define SRAM_RTT_SLEEP_FLAG_ADDR (SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_ADDR + SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_SIZE) +#define SRAM_RTT_SLEEP_FLAG_SIZE (32) + +/* LDSP Awake Flag */ +#define MEMORY_AXI_LDSP_AWAKE_ADDR (SRAM_RTT_SLEEP_FLAG_ADDR + SRAM_RTT_SLEEP_FLAG_SIZE) +#define MEMORY_AXI_LDSP_AWAKE_SIZE (4) + +#define NVUPDATE_SUCCESS 0x5555AAAA +#define NVUPDATE_FAILURE 0xAAAA5555 + +/* + * Low Power Mode Region + */ +#define PWRCTRL_ACPU_ASM_MEM_BASE (SRAM_PM_ADDR) +#define PWRCTRL_ACPU_ASM_MEM_SIZE (SRAM_PM_SIZE) + +#define PWRCTRL_ACPU_ASM_CODE_BASE (PWRCTRL_ACPU_ASM_MEM_BASE + 0x200) +#define PWRCTRL_ACPU_ASM_DATA_BASE (PWRCTRL_ACPU_ASM_MEM_BASE + 0xE00) +#define PWRCTRL_ACPU_ASM_DATA_SIZE (0xE00) + +#define PWRCTRL_ACPU_ASM_D_C0_ADDR (PWRCTRL_ACPU_ASM_DATA_BASE) +#define PWRCTRL_ACPU_ASM_D_C0_MMU_PARA_AD (PWRCTRL_ACPU_ASM_DATA_BASE + 0) +#define PWRCTRL_ACPU_ASM_D_ARM_PARA_AD (PWRCTRL_ACPU_ASM_DATA_BASE + 0x20) +#define PWRCTRL_ACPU_ASM_D_COMM_ADDR (PWRCTRL_ACPU_ASM_DATA_BASE + 0x700) + +#define PWRCTRL_ACPU_REBOOT (PWRCTRL_ACPU_ASM_D_COMM_ADDR) +#define PWRCTRL_ACPU_REBOOT_SIZE (0x200) +#define PWRCTRL_ACPU_ASM_SLICE_BAK_ADDR (PWRCTRL_ACPU_REBOOT + PWRCTRL_ACPU_REBOOT_SIZE) +#define PWRCTRL_ACPU_ASM_SLICE_BAK_SIZE (4) +#define PWRCTRL_ACPU_ASM_DEBUG_FLAG_ADDR (PWRCTRL_ACPU_ASM_SLICE_BAK_ADDR + PWRCTRL_ACPU_ASM_SLICE_BAK_SIZE) +#define PWRCTRL_ACPU_ASM_DEBUG_FLAG_SIZE (4) +#define EXCH_A_CORE_POWRCTRL_CONV_ADDR (PWRCTRL_ACPU_ASM_DEBUG_FLAG_ADDR + PWRCTRL_ACPU_ASM_DEBUG_FLAG_SIZE) +#define EXCH_A_CORE_POWRCTRL_CONV_SIZE (4) + +#define MEMORY_AXI_CPU_IDLE_ADDR (EXCH_A_CORE_POWRCTRL_CONV_ADDR + EXCH_A_CORE_POWRCTRL_CONV_SIZE) +#define MEMORY_AXI_CPU_IDLE_SIZE (4) + +#define MEMORY_AXI_CUR_FREQ_ADDR (MEMORY_AXI_CPU_IDLE_ADDR + MEMORY_AXI_CPU_IDLE_SIZE) +#define MEMORY_AXI_CUR_FREQ_SIZE (12) + +#define MEMORY_AXI_ACPU_FREQ_VOL_ADDR (MEMORY_AXI_CUR_FREQ_ADDR + MEMORY_AXI_CUR_FREQ_SIZE) +#define MEMORY_AXI_ACPU_FREQ_VOL_SIZE (16 + 28) + +#define MEMORY_AXI_DDR_FREQ_VOL_ADDR (MEMORY_AXI_ACPU_FREQ_VOL_ADDR + MEMORY_AXI_ACPU_FREQ_VOL_SIZE) +#define MEMORY_AXI_DDR_FREQ_VOL_SIZE (16 + 28) + +#define MEMORY_AXI_ACPU_FIQ_TEST_ADDR (MEMORY_AXI_DDR_FREQ_VOL_ADDR + MEMORY_AXI_DDR_FREQ_VOL_SIZE) +#define MEMORY_AXI_ACPU_FIQ_TEST_SIZE (12) + +#define MEMORY_AXI_ACPU_FIQ_CPU_INFO_ADDR (MEMORY_AXI_ACPU_FIQ_TEST_ADDR + MEMORY_AXI_ACPU_FIQ_TEST_SIZE) +#define MEMORY_AXI_ACPU_FIQ_CPU_INFO_SIZE (24) + +#define MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_ADDR (MEMORY_AXI_ACPU_FIQ_CPU_INFO_ADDR + MEMORY_AXI_ACPU_FIQ_CPU_INFO_SIZE) +#define MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_SIZE (20) + +#define MEMORY_FREQDUMP_ADDR (MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_ADDR + MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_SIZE) +#define MEMORY_FREQDUMP_SIZE (64) + +#define MEMORY_AXI_CCPU_LOG_ADDR (MEMORY_FREQDUMP_ADDR + MEMORY_FREQDUMP_SIZE) +#define MEMORY_AXI_CCPU_LOG_SIZE (4) + +#define MEMORY_AXI_MCU_LOG_ADDR (MEMORY_AXI_CCPU_LOG_ADDR + MEMORY_AXI_CCPU_LOG_SIZE) +#define MEMORY_AXI_MCU_LOG_SIZE (4) + +#define MEMORY_AXI_SEC_CORE_BOOT_ADDR (MEMORY_AXI_MCU_LOG_ADDR + MEMORY_AXI_MCU_LOG_SIZE) +#define MEMORY_AXI_SEC_CORE_BOOT_SIZE (4) + +#define MEMORY_AXI_BBP_PS_VOTE_FLAG_ADDR (MEMORY_AXI_SEC_CORE_BOOT_ADDR + MEMORY_AXI_SEC_CORE_BOOT_SIZE) +#define MEMORY_AXI_BBP_PS_VOTE_FLAG_SIZE (0x4) + +#define POLICY_AREA_RESERVED (MEMORY_AXI_BBP_PS_VOTE_FLAG_ADDR + MEMORY_AXI_BBP_PS_VOTE_FLAG_SIZE) +#define POLICY_AREA_RESERVED_SIZE (12) + +#define DDR_POLICY_VALID_MAGIC (POLICY_AREA_RESERVED + POLICY_AREA_RESERVED_SIZE) +#define DDR_POLICY_VALID_MAGIC_SIZE (4) + +#define DDR_POLICY_MAX_NUM (DDR_POLICY_VALID_MAGIC + DDR_POLICY_VALID_MAGIC_SIZE) +#define DDR_POLICY_MAX_NUM_SIZE (4) + +#define DDR_POLICY_SUPPORT_NUM (DDR_POLICY_MAX_NUM + DDR_POLICY_MAX_NUM_SIZE) +#define DDR_POLICY_SUPPORT_NUM_SIZE (4) + +#define DDR_POLICY_CUR_POLICY (DDR_POLICY_SUPPORT_NUM + DDR_POLICY_SUPPORT_NUM_SIZE) +#define DDR_POLICY_CUR_POLICY_SIZE (4) + +#define ACPU_POLICY_VALID_MAGIC (DDR_POLICY_CUR_POLICY + DDR_POLICY_CUR_POLICY_SIZE) +#define ACPU_POLICY_VALID_MAGIC_SIZE (4) + +#define ACPU_POLICY_MAX_NUM (ACPU_POLICY_VALID_MAGIC + ACPU_POLICY_VALID_MAGIC_SIZE) +#define ACPU_POLICY_MAX_NUM_SIZE (4) + +#define ACPU_POLICY_SUPPORT_NUM (ACPU_POLICY_MAX_NUM + ACPU_POLICY_MAX_NUM_SIZE) +#define ACPU_POLICY_SUPPORT_NUM_SIZE (4) + +#define ACPU_POLICY_CUR_POLICY (ACPU_POLICY_SUPPORT_NUM + ACPU_POLICY_SUPPORT_NUM_SIZE) +#define ACPU_POLICY_CUR_POLICY_SIZE (4) + +#define LPDDR_OPTION_ADDR (ACPU_POLICY_CUR_POLICY + ACPU_POLICY_CUR_POLICY_SIZE) +#define LPDDR_OPTION_SIZE (4) + +#define MEMORY_AXI_DDR_DDL_ADDR (LPDDR_OPTION_ADDR + LPDDR_OPTION_SIZE) +#define MEMORY_AXI_DDR_DDL_SIZE (0x2B0) + +#define DDR_TEST_DFS_ADDR (MEMORY_AXI_DDR_DDL_ADDR + MEMORY_AXI_DDR_DDL_SIZE) +#define DDR_TEST_DFS_ADDR_SIZE (4) + +#define DDR_TEST_DFS_TIMES_ADDR (DDR_TEST_DFS_ADDR + DDR_TEST_DFS_ADDR_SIZE) +#define DDR_TEST_DFS_TIMES_ADDR_SIZE (4) + +#define DDR_TEST_QOS_ADDR (DDR_TEST_DFS_TIMES_ADDR + DDR_TEST_DFS_TIMES_ADDR_SIZE) +#define DDR_TEST_QOS_ADDR_SIZE (4) + +#define DDR_TEST_FUN_ADDR (DDR_TEST_QOS_ADDR + DDR_TEST_QOS_ADDR_SIZE) +#define DDR_TEST_FUN_ADDR_SIZE (4) + +#define BOARD_TYPE_ADDR (DDR_TEST_FUN_ADDR + DDR_TEST_FUN_ADDR_SIZE) +#define BOARD_ADDR_SIZE (4) +#define DDR_DFS_FREQ_ADDR (BOARD_TYPE_ADDR + BOARD_ADDR_SIZE) +#define DDR_DFS_FREQ_SIZE (4) + +#define ACPU_DFS_FREQ_ADDR (DDR_DFS_FREQ_ADDR + DDR_DFS_FREQ_SIZE) +#define ACPU_DFS_FREQ_ADDR_SIZE (12) + +#define ACPU_CHIP_MAX_FREQ (ACPU_DFS_FREQ_ADDR + ACPU_DFS_FREQ_ADDR_SIZE) +#define ACPU_CHIP_MAX_FREQ_SIZE (4) + +#define MEMORY_MEDPLL_STATE_ADDR (ACPU_CHIP_MAX_FREQ + ACPU_CHIP_MAX_FREQ_SIZE) +#define MEMORY_MEDPLL_STATE_SIZE (8) + +#define ACPU_CORE_BITS_ADDR (MEMORY_MEDPLL_STATE_ADDR + MEMORY_MEDPLL_STATE_SIZE) +#define ACPU_CORE_BITS_SIZE (4) + +#define ACPU_CLUSTER_IDLE_ADDR (ACPU_CORE_BITS_ADDR + ACPU_CORE_BITS_SIZE) +#define ACPU_CLUSTER_IDLE_SIZE (4) + +#define ACPU_A53_FLAGS_ADDR (ACPU_CLUSTER_IDLE_ADDR + ACPU_CLUSTER_IDLE_SIZE) +#define ACPU_A53_FLAGS_SIZE (4) +#define PWRCTRL_AXI_RESERVED_ADDR (ACPU_A53_FLAGS_ADDR + ACPU_A53_FLAGS_SIZE) + +#endif /* __SRAM_MAP_H__ */
When load mcu binary, need map the sram region so that can copy mcu binary into the sram.
And currently BL30 binary has not been used by hikey platform, so can use BL30 to store mcu binary. Add the BL30 info in the io storage structure.
Signed-off-by: Leo Yan leo.yan@linaro.org --- plat/hikey/aarch64/hikey_common.c | 6 ++++++ plat/hikey/bl2_plat_setup.c | 40 +++++++++++++++++++++++++++++++++++++++ plat/hikey/hikey_def.h | 3 +++ plat/hikey/include/platform_def.h | 8 +++++++- plat/hikey/plat_io_storage.c | 10 ++++++++++ 5 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/plat/hikey/aarch64/hikey_common.c b/plat/hikey/aarch64/hikey_common.c index d90ab9e..055dde8 100644 --- a/plat/hikey/aarch64/hikey_common.c +++ b/plat/hikey/aarch64/hikey_common.c @@ -52,6 +52,10 @@ 0x1000, \ MT_DEVICE | MT_RW | MT_NS)
+#define MAP_SRAM MAP_REGION_FLAT(SRAM_BASE, \ + SRAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + /* * Table of regions for different BL stages to map using the MMU. * This doesn't include Trusted RAM as the 'mem_layout' argument passed to @@ -62,6 +66,7 @@ static const mmap_region_t hikey_mmap[] = { MAP_DEVICE, MAP_NS_DRAM, MAP_ROM_PARAM, + MAP_SRAM, {0} }; #endif @@ -69,6 +74,7 @@ static const mmap_region_t hikey_mmap[] = { static const mmap_region_t hikey_mmap[] = { MAP_DEVICE, MAP_NS_DRAM, + MAP_SRAM, {0} }; #endif diff --git a/plat/hikey/bl2_plat_setup.c b/plat/hikey/bl2_plat_setup.c index 7055504..631a3bf 100644 --- a/plat/hikey/bl2_plat_setup.c +++ b/plat/hikey/bl2_plat_setup.c @@ -38,6 +38,8 @@ #include <platform.h> #include <platform_def.h> #include <string.h> +#include <mmio.h> +#include <hi6220.h> #include "hikey_def.h" #include "hikey_private.h"
@@ -190,6 +192,10 @@ void bl2_plat_arch_setup(void) ******************************************************************************/ void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo) { + bl30_meminfo->total_base = 0x01000000; + bl30_meminfo->total_size = 0x01000000; + bl30_meminfo->free_base = 0x01000000; + bl30_meminfo->free_size = 0x01000000; }
/******************************************************************************* @@ -198,6 +204,40 @@ void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo) ******************************************************************************/ int bl2_plat_handle_bl30(image_info_t *bl30_image_info) { + int *buf = (int *)bl30_image_info->image_base; + + INFO("%s: [%x] %x %x %x %x\n", + __func__, buf, buf[0], buf[1], buf[2], buf[3]); + + buf += 50; + INFO("%s: [%x] %x %x %x %x\n", + __func__, buf, buf[0], buf[1], buf[2], buf[3]); + + buf += 50; + INFO("%s: [%x] %x %x %x %x\n", + __func__, buf, buf[0], buf[1], buf[2], buf[3]); + + buf = (int *)(bl30_image_info->image_base + + bl30_image_info->image_size); + buf -= 4; + INFO("%s: [%x] %x %x %x %x\n", + __func__, buf, buf[0], buf[1], buf[2], buf[3]); + + /* enable mcu sram */ + hisi_mcu_enable_sram(); + + /* load mcu binary to sram */ + hisi_mcu_load_image(bl30_image_info->image_base, + bl30_image_info->image_size); + + /* let mcu to run */ + hisi_mcu_start_run(); + + INFO("%s: mcu pc is %x\n", + __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2)); + + INFO("%s: AO_SC_PERIPH_CLKSTAT4 is %x\n", + __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4)); return 0; }
diff --git a/plat/hikey/hikey_def.h b/plat/hikey/hikey_def.h index b26af68..fc5901e 100644 --- a/plat/hikey/hikey_def.h +++ b/plat/hikey/hikey_def.h @@ -42,6 +42,9 @@ #define XG2RAM0_BASE 0xF9800000 #define XG2RAM0_SIZE 0x00400000
+#define SRAM_BASE 0xFFF80000 +#define SRAM_SIZE 0x00012000 + /* * DRAM at 0x0000_0000 is divided in two regions: * - Secure DRAM (default is the top 16MB except for the last 2MB, which are diff --git a/plat/hikey/include/platform_def.h b/plat/hikey/include/platform_def.h index e8f16b7..46a2fcd 100644 --- a/plat/hikey/include/platform_def.h +++ b/plat/hikey/include/platform_def.h @@ -132,6 +132,12 @@ #define BL31_LIMIT (BL31_BASE + 0x40000)
/******************************************************************************* + * BL3-1 specific defines. + ******************************************************************************/ +#define BL30_BASE (0x01000000) /* 0xf989_8000 */ +#define BL30_LIMIT (0x01000000 + 0x40000) + +/******************************************************************************* * Load address of BL3-3 in the HiKey port ******************************************************************************/ #define NS_IMAGE_OFFSET (DRAM_BASE + 0x37000000) /* 880MB */ @@ -142,7 +148,7 @@ #define ADDR_SPACE_SIZE (1ull << 32)
#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31 -# define MAX_XLAT_TABLES 3 +# define MAX_XLAT_TABLES 4 #endif
#define MAX_MMAP_REGIONS 16 diff --git a/plat/hikey/plat_io_storage.c b/plat/hikey/plat_io_storage.c index 98f5845..59d4725 100644 --- a/plat/hikey/plat_io_storage.c +++ b/plat/hikey/plat_io_storage.c @@ -95,6 +95,11 @@ static const io_file_spec_t bl2_file_spec = { .mode = FOPEN_MODE_RB };
+static const io_file_spec_t bl30_file_spec = { + .path = BL30_IMAGE_NAME, + .mode = FOPEN_MODE_RB +}; + static const io_file_spec_t bl31_file_spec = { .path = BL31_IMAGE_NAME, .mode = FOPEN_MODE_RB @@ -144,6 +149,11 @@ static const struct plat_io_policy policies[] = { (uintptr_t)&bl2_file_spec, open_fip }, { + BL30_IMAGE_NAME, + &fip_dev_handle, + (uintptr_t)&bl30_file_spec, + open_fip + }, { BL31_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl31_file_spec,
On Wed, Mar 25, 2015 at 12:26 PM, Leo Yan leo.yan@linaro.org wrote:
When load mcu binary, need map the sram region so that can copy mcu binary into the sram.
And currently BL30 binary has not been used by hikey platform, so can use BL30 to store mcu binary. Add the BL30 info in the io storage structure.
Signed-off-by: Leo Yan leo.yan@linaro.org
plat/hikey/aarch64/hikey_common.c | 6 ++++++ plat/hikey/bl2_plat_setup.c | 40 +++++++++++++++++++++++++++++++++++++++ plat/hikey/hikey_def.h | 3 +++ plat/hikey/include/platform_def.h | 8 +++++++- plat/hikey/plat_io_storage.c | 10 ++++++++++ 5 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/plat/hikey/aarch64/hikey_common.c b/plat/hikey/aarch64/hikey_common.c index d90ab9e..055dde8 100644 --- a/plat/hikey/aarch64/hikey_common.c +++ b/plat/hikey/aarch64/hikey_common.c @@ -52,6 +52,10 @@ 0x1000, \ MT_DEVICE | MT_RW | MT_NS)
+#define MAP_SRAM MAP_REGION_FLAT(SRAM_BASE, \
SRAM_SIZE, \MT_DEVICE | MT_RW | MT_SECURE)/*
- Table of regions for different BL stages to map using the MMU.
- This doesn't include Trusted RAM as the 'mem_layout' argument passed to
@@ -62,6 +66,7 @@ static const mmap_region_t hikey_mmap[] = { MAP_DEVICE, MAP_NS_DRAM, MAP_ROM_PARAM,
MAP_SRAM, {0}}; #endif @@ -69,6 +74,7 @@ static const mmap_region_t hikey_mmap[] = { static const mmap_region_t hikey_mmap[] = { MAP_DEVICE, MAP_NS_DRAM,
MAP_SRAM, {0}}; #endif diff --git a/plat/hikey/bl2_plat_setup.c b/plat/hikey/bl2_plat_setup.c index 7055504..631a3bf 100644 --- a/plat/hikey/bl2_plat_setup.c +++ b/plat/hikey/bl2_plat_setup.c @@ -38,6 +38,8 @@ #include <platform.h> #include <platform_def.h> #include <string.h> +#include <mmio.h> +#include <hi6220.h> #include "hikey_def.h" #include "hikey_private.h"
@@ -190,6 +192,10 @@ void bl2_plat_arch_setup(void)
******************************************************************************/ void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo) {
bl30_meminfo->total_base = 0x01000000;bl30_meminfo->total_size = 0x01000000;bl30_meminfo->free_base = 0x01000000;bl30_meminfo->free_size = 0x01000000;}
Based on comment below, is this 0x01000000 or 0xf9898000?
/******************************************************************************* @@ -198,6 +204,40 @@ void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo)
******************************************************************************/ int bl2_plat_handle_bl30(image_info_t *bl30_image_info) {
int *buf = (int *)bl30_image_info->image_base;INFO("%s: [%x] %x %x %x %x\n",__func__, buf, buf[0], buf[1], buf[2], buf[3]);buf += 50;INFO("%s: [%x] %x %x %x %x\n",__func__, buf, buf[0], buf[1], buf[2], buf[3]);buf += 50;INFO("%s: [%x] %x %x %x %x\n",__func__, buf, buf[0], buf[1], buf[2], buf[3]);buf = (int *)(bl30_image_info->image_base +bl30_image_info->image_size);buf -= 4;INFO("%s: [%x] %x %x %x %x\n",__func__, buf, buf[0], buf[1], buf[2], buf[3]);/* enable mcu sram */hisi_mcu_enable_sram();/* load mcu binary to sram */hisi_mcu_load_image(bl30_image_info->image_base,bl30_image_info->image_size);/* let mcu to run */hisi_mcu_start_run();INFO("%s: mcu pc is %x\n",__func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2));INFO("%s: AO_SC_PERIPH_CLKSTAT4 is %x\n",__func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4)); return 0;}
diff --git a/plat/hikey/hikey_def.h b/plat/hikey/hikey_def.h index b26af68..fc5901e 100644 --- a/plat/hikey/hikey_def.h +++ b/plat/hikey/hikey_def.h @@ -42,6 +42,9 @@ #define XG2RAM0_BASE 0xF9800000 #define XG2RAM0_SIZE 0x00400000
+#define SRAM_BASE 0xFFF80000 +#define SRAM_SIZE 0x00012000
/*
- DRAM at 0x0000_0000 is divided in two regions:
- Secure DRAM (default is the top 16MB except for the last 2MB,
which are diff --git a/plat/hikey/include/platform_def.h b/plat/hikey/include/platform_def.h index e8f16b7..46a2fcd 100644 --- a/plat/hikey/include/platform_def.h +++ b/plat/hikey/include/platform_def.h @@ -132,6 +132,12 @@ #define BL31_LIMIT (BL31_BASE + 0x40000)
/*******************************************************************************
- BL3-1 specific defines.
******************************************************************************/ +#define BL30_BASE (0x01000000) /* 0xf989_8000 */
The comment is confusing. Is this 0x01000000 or 0xf9898000?
+#define BL30_LIMIT (0x01000000 + 0x40000)
+/*******************************************************************************
- Load address of BL3-3 in the HiKey port
******************************************************************************/ #define NS_IMAGE_OFFSET (DRAM_BASE + 0x37000000) /* 880MB */ @@ -142,7 +148,7 @@ #define ADDR_SPACE_SIZE (1ull << 32)
#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31 -# define MAX_XLAT_TABLES 3 +# define MAX_XLAT_TABLES 4 #endif
#define MAX_MMAP_REGIONS 16 diff --git a/plat/hikey/plat_io_storage.c b/plat/hikey/plat_io_storage.c index 98f5845..59d4725 100644 --- a/plat/hikey/plat_io_storage.c +++ b/plat/hikey/plat_io_storage.c @@ -95,6 +95,11 @@ static const io_file_spec_t bl2_file_spec = { .mode = FOPEN_MODE_RB };
+static const io_file_spec_t bl30_file_spec = {
.path = BL30_IMAGE_NAME,.mode = FOPEN_MODE_RB+};
static const io_file_spec_t bl31_file_spec = { .path = BL31_IMAGE_NAME, .mode = FOPEN_MODE_RB @@ -144,6 +149,11 @@ static const struct plat_io_policy policies[] = { (uintptr_t)&bl2_file_spec, open_fip }, {
BL30_IMAGE_NAME,&fip_dev_handle,(uintptr_t)&bl30_file_spec,open_fip}, { BL31_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl31_file_spec,-- 1.9.1
Dev mailing list Dev@lists.96boards.org https://lists.96boards.org/mailman/listinfo/dev
On Wed, Mar 25, 2015 at 02:38:49PM +0900, Victor Chong wrote:
On Wed, Mar 25, 2015 at 12:26 PM, Leo Yan leo.yan@linaro.org wrote:
When load mcu binary, need map the sram region so that can copy mcu binary into the sram.
And currently BL30 binary has not been used by hikey platform, so can use BL30 to store mcu binary. Add the BL30 info in the io storage structure.
Signed-off-by: Leo Yan leo.yan@linaro.org
plat/hikey/aarch64/hikey_common.c | 6 ++++++ plat/hikey/bl2_plat_setup.c | 40 +++++++++++++++++++++++++++++++++++++++ plat/hikey/hikey_def.h | 3 +++ plat/hikey/include/platform_def.h | 8 +++++++- plat/hikey/plat_io_storage.c | 10 ++++++++++ 5 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/plat/hikey/aarch64/hikey_common.c b/plat/hikey/aarch64/hikey_common.c index d90ab9e..055dde8 100644 --- a/plat/hikey/aarch64/hikey_common.c +++ b/plat/hikey/aarch64/hikey_common.c @@ -52,6 +52,10 @@ 0x1000, \ MT_DEVICE | MT_RW | MT_NS)
+#define MAP_SRAM MAP_REGION_FLAT(SRAM_BASE, \
SRAM_SIZE, \MT_DEVICE | MT_RW | MT_SECURE)/*
- Table of regions for different BL stages to map using the MMU.
- This doesn't include Trusted RAM as the 'mem_layout' argument passed to
@@ -62,6 +66,7 @@ static const mmap_region_t hikey_mmap[] = { MAP_DEVICE, MAP_NS_DRAM, MAP_ROM_PARAM,
MAP_SRAM, {0}}; #endif @@ -69,6 +74,7 @@ static const mmap_region_t hikey_mmap[] = { static const mmap_region_t hikey_mmap[] = { MAP_DEVICE, MAP_NS_DRAM,
MAP_SRAM, {0}}; #endif diff --git a/plat/hikey/bl2_plat_setup.c b/plat/hikey/bl2_plat_setup.c index 7055504..631a3bf 100644 --- a/plat/hikey/bl2_plat_setup.c +++ b/plat/hikey/bl2_plat_setup.c @@ -38,6 +38,8 @@ #include <platform.h> #include <platform_def.h> #include <string.h> +#include <mmio.h> +#include <hi6220.h> #include "hikey_def.h" #include "hikey_private.h"
@@ -190,6 +192,10 @@ void bl2_plat_arch_setup(void)
******************************************************************************/ void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo) {
bl30_meminfo->total_base = 0x01000000;bl30_meminfo->total_size = 0x01000000;bl30_meminfo->free_base = 0x01000000;bl30_meminfo->free_size = 0x01000000;}
Based on comment below, is this 0x01000000 or 0xf9898000?
At beginning i wanted to use 0xf9898000 in xg2ram0, but found after the data loaded into this area and later read back all values are zero.
So change to use 0x0100_0000 as temporary buffer for mcu image, ATF will load the sections into other memory regions, so 0x0100_0000 will not be used anymore.
Will check size of xg2ram0 w/t Hisilicon and fix in next version's patch.
/******************************************************************************* @@ -198,6 +204,40 @@ void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo)
******************************************************************************/ int bl2_plat_handle_bl30(image_info_t *bl30_image_info) {
int *buf = (int *)bl30_image_info->image_base;INFO("%s: [%x] %x %x %x %x\n",__func__, buf, buf[0], buf[1], buf[2], buf[3]);buf += 50;INFO("%s: [%x] %x %x %x %x\n",__func__, buf, buf[0], buf[1], buf[2], buf[3]);buf += 50;INFO("%s: [%x] %x %x %x %x\n",__func__, buf, buf[0], buf[1], buf[2], buf[3]);buf = (int *)(bl30_image_info->image_base +bl30_image_info->image_size);buf -= 4;INFO("%s: [%x] %x %x %x %x\n",__func__, buf, buf[0], buf[1], buf[2], buf[3]);/* enable mcu sram */hisi_mcu_enable_sram();/* load mcu binary to sram */hisi_mcu_load_image(bl30_image_info->image_base,bl30_image_info->image_size);/* let mcu to run */hisi_mcu_start_run();INFO("%s: mcu pc is %x\n",__func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2));INFO("%s: AO_SC_PERIPH_CLKSTAT4 is %x\n",__func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4)); return 0;}
diff --git a/plat/hikey/hikey_def.h b/plat/hikey/hikey_def.h index b26af68..fc5901e 100644 --- a/plat/hikey/hikey_def.h +++ b/plat/hikey/hikey_def.h @@ -42,6 +42,9 @@ #define XG2RAM0_BASE 0xF9800000 #define XG2RAM0_SIZE 0x00400000
+#define SRAM_BASE 0xFFF80000 +#define SRAM_SIZE 0x00012000
/*
- DRAM at 0x0000_0000 is divided in two regions:
- Secure DRAM (default is the top 16MB except for the last 2MB,
which are diff --git a/plat/hikey/include/platform_def.h b/plat/hikey/include/platform_def.h index e8f16b7..46a2fcd 100644 --- a/plat/hikey/include/platform_def.h +++ b/plat/hikey/include/platform_def.h @@ -132,6 +132,12 @@ #define BL31_LIMIT (BL31_BASE + 0x40000)
/*******************************************************************************
- BL3-1 specific defines.
******************************************************************************/ +#define BL30_BASE (0x01000000) /* 0xf989_8000 */
The comment is confusing. Is this 0x01000000 or 0xf9898000?
+#define BL30_LIMIT (0x01000000 + 0x40000)
+/*******************************************************************************
- Load address of BL3-3 in the HiKey port
******************************************************************************/ #define NS_IMAGE_OFFSET (DRAM_BASE + 0x37000000) /* 880MB */ @@ -142,7 +148,7 @@ #define ADDR_SPACE_SIZE (1ull << 32)
#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31 -# define MAX_XLAT_TABLES 3 +# define MAX_XLAT_TABLES 4 #endif
#define MAX_MMAP_REGIONS 16 diff --git a/plat/hikey/plat_io_storage.c b/plat/hikey/plat_io_storage.c index 98f5845..59d4725 100644 --- a/plat/hikey/plat_io_storage.c +++ b/plat/hikey/plat_io_storage.c @@ -95,6 +95,11 @@ static const io_file_spec_t bl2_file_spec = { .mode = FOPEN_MODE_RB };
+static const io_file_spec_t bl30_file_spec = {
.path = BL30_IMAGE_NAME,.mode = FOPEN_MODE_RB+};
static const io_file_spec_t bl31_file_spec = { .path = BL31_IMAGE_NAME, .mode = FOPEN_MODE_RB @@ -144,6 +149,11 @@ static const struct plat_io_policy policies[] = { (uintptr_t)&bl2_file_spec, open_fip }, {
BL30_IMAGE_NAME,&fip_dev_handle,(uintptr_t)&bl30_file_spec,open_fip}, { BL31_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl31_file_spec,-- 1.9.1
Dev mailing list Dev@lists.96boards.org https://lists.96boards.org/mailman/listinfo/dev
If io storage has not been initialized, then it will fail to load BL30 binary. So change the code to load BL30 binary after io storage has been initialized successfully.
Signed-off-by: Leo Yan leo.yan@linaro.org --- bl2/bl2_main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c index 29ca0a5..f6b93b7 100644 --- a/bl2/bl2_main.c +++ b/bl2/bl2_main.c @@ -411,6 +411,9 @@ void bl2_main(void) } #endif /* TRUSTED_BOARD_BOOT */
+ /* Perform platform setup in BL2 after loading BL3-0 */ + bl2_platform_setup(); + /* * Load the subsequent bootloader images */ @@ -420,9 +423,6 @@ void bl2_main(void) panic(); }
- /* Perform platform setup in BL2 after loading BL3-0 */ - bl2_platform_setup(); - /* * Get a pointer to the memory the platform has set aside to pass * information to BL3-1.
Signed-off-by: Leo Yan leo.yan@linaro.org --- plat/hikey/bl1_plat_setup.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/plat/hikey/bl1_plat_setup.c b/plat/hikey/bl1_plat_setup.c index 6ccac43..c1fda51 100644 --- a/plat/hikey/bl1_plat_setup.c +++ b/plat/hikey/bl1_plat_setup.c @@ -171,10 +171,11 @@ static void hi6220_pmussi_init(void) * After reset, PMUSSI stays in reset mode. * Now make it out of reset. */ - mmio_write_32(AO_SC_PERIPH_RSTDIS4, AO_SC_PERIPH_CLKEN4_PMUSSI); + mmio_write_32(AO_SC_PERIPH_RSTDIS4, + AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N); do { data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); - } while (data & AO_SC_PERIPH_CLKEN4_PMUSSI); + } while (data & AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N);
/* set PMU SSI clock latency for read operation */ data = mmio_read_32(AO_SC_MCU_SUBSYS_CTRL3); @@ -183,9 +184,10 @@ static void hi6220_pmussi_init(void) mmio_write_32(AO_SC_MCU_SUBSYS_CTRL3, data);
/* enable PMUSSI clock */ - data = AO_SC_PERIPH_CLKEN5_PMUSSI_CCPU | AO_SC_PERIPH_CLKEN5_PMUSSI_MCU; + data = AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU | + AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU; mmio_write_32(AO_SC_PERIPH_CLKEN5, data); - data = AO_SC_PERIPH_CLKEN4_PMUSSI; + data = AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI; mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
/* output high on gpio0 */
Before load mcu binary, need initialize the sram region so that mcu can read related opp info; otherwise mcu cannot work well and will reset the SoC.
The dvfs driver will set opps info into sram and will be used later by mcu firmware.
Signed-off-by: Leo Yan leo.yan@linaro.org --- plat/hikey/drivers/hisi_dvfs.c | 775 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 775 insertions(+) create mode 100644 plat/hikey/drivers/hisi_dvfs.c
diff --git a/plat/hikey/drivers/hisi_dvfs.c b/plat/hikey/drivers/hisi_dvfs.c new file mode 100644 index 0000000..c327b61 --- /dev/null +++ b/plat/hikey/drivers/hisi_dvfs.c @@ -0,0 +1,775 @@ +/* + * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. + * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch_helpers.h> +#include <assert.h> +#include <bl_common.h> +#include <console.h> +#include <debug.h> +#include <partitions.h> +#include <platform.h> +#include <platform_def.h> +#include <string.h> +#include <mmio.h> +#include <hi6220.h> +#include <hi6553.h> + +#define ACPU_FREQ_MAX_NUM 5 +#define ACPU_OPP_NUM 7 + +#define ACPU_VALID_VOLTAGE_MAGIC (0x5A5AC5C5) + +#define ACPU_WAIT_TIMEOUT (200) +#define ACPU_WAIT_FOR_WFI_TIMOUT (2000) +#define ACPU_DFS_STATE_CNT (0x10000) + +struct acpu_dvfs_sram_stru { + unsigned int magic; + unsigned int support_freq_num; + unsigned int support_freq_max; + unsigned int start_prof; + unsigned int vol[ACPU_OPP_NUM]; +}; + +struct acpu_volt_cal_para { + unsigned int freq; + unsigned int ul_vol; + unsigned int dl_vol; + unsigned int core_ref_hpm; +}; + +struct ddr_volt_cal_para { + unsigned int freq; + unsigned int ul_vol; + unsigned int dl_vol; + unsigned int ddr_ref_hpm; +}; + +struct acpu_dvfs_opp_para { + unsigned int freq; + unsigned int acpu_clk_profile0; + unsigned int acpu_clk_profile1; + unsigned int acpu_vol_profile; + unsigned int acpu_pll_freq; + unsigned int acpu_pll_frac; +}; + +unsigned int efuse_acpu_freq[]= { + 1200000, 1250000, 1300000, 1350000, + 1400000, 1450000, 1500000, 1550000, + 1600000, 1650000, 1700000, 1750000, + 1800000, 1850000, 1900000, 1950000, +}; + +struct acpu_dvfs_opp_para hi6220_acpu_profile[] = { + { 208000, 0x61E5, 0x022, 0x3A, 0x5220102B, 0x05555555 }, + { 432000, 0x10A6, 0x121, 0x3A, 0x5120102D, 0x10000005 }, + { 729000, 0x2283, 0x100, 0x4A, 0x51101026, 0x10000005 }, + { 960000, 0x1211, 0x100, 0x5B, 0x51101032, 0x10000005 }, + { 1200000, 0x1211, 0x100, 0x6B, 0x5110207D, 0x10000005 }, + { 1400000, 0x1211, 0x100, 0x6B, 0x51101049, 0x10000005 }, + { 1500000, 0x1211, 0x100, 0x6B, 0x51101049, 0x10000005 }, +}; + +struct acpu_dvfs_opp_para *acpu_dvfs_profile = hi6220_acpu_profile; +struct acpu_dvfs_sram_stru *acpu_dvfs_sram_buf = + (struct acpu_dvfs_sram_stru *)MEMORY_AXI_ACPU_FREQ_VOL_ADDR; + +static inline void write_reg_mask(uintptr_t addr, + uint32_t val, uint32_t mask) +{ + uint32_t reg; + + reg = mmio_read_32(addr); + reg = (reg & ~(mask)) | val; + mmio_write_32(addr, reg); +} + +static inline uint32_t read_reg_mask(uintptr_t addr, + uint32_t mask, uint32_t offset) +{ + uint32_t reg; + + reg = mmio_read_32(addr); + reg &= (mask << offset); + return (reg >> offset); +} + +static int acpu_dvfs_syspll_cfg(unsigned int prof_id) +{ + uint32_t reg0 = 0; + uint32_t count = 0; + uint32_t clk_div_status = 0; + + /* + * step 1: + * - ACPUSYSPLLCFG.acpu_subsys_clk_div_sw = 0x3; + * - ACPUSYSPLLCFG.acpu_syspll_clken_cfg = 0x1; + */ + write_reg_mask(PMCTRL_ACPUSYSPLLCFG, 0x3 << 12, 0x3 << 12); + write_reg_mask(PMCTRL_ACPUSYSPLLCFG, 0x1 << 4, 0x1 << 4); + + /* + * step 2: + * - ACPUSYSPLLCFG.acpu_syspll_div_cfg: + * 208MHz, set to 0x5; + * 500MHz, set to 0x2; + * other opps set to 0x1 + */ + if (prof_id == 0) + write_reg_mask(PMCTRL_ACPUSYSPLLCFG, 0x5 << 0, 0x7 << 0); + else if (prof_id == 1) + write_reg_mask(PMCTRL_ACPUSYSPLLCFG, 0x2 << 0, 0x7 << 0); + else + write_reg_mask(PMCTRL_ACPUSYSPLLCFG, 0x1 << 0, 0x7 << 0); + + /* + * step 3: + * - Polling ACPU_SC_CPU_STAT.clk_div_status_vd == 0x3; + * - ACPU_SC_VD_CTRL.tune_en_dif = 0 + * - ACPU_SC_VD_CTRL.tune_en_int = 0 + * - PMCTRL_ACPUCLKDIV.acpu_ddr_clk_div_cfg = 0x1 + * - PMCTRL_ACPUPLLSEL.acpu_pllsw_cfg = 0x1 + */ + clk_div_status = 0x3; + do { + reg0 = read_reg_mask(ACPU_SC_CPU_STAT, 0x3, 20); + if ((count++) > ACPU_DFS_STATE_CNT) { + ERROR("%s: clk div status timeout!\n", __func__); + return -1; + } + } while(clk_div_status != reg0); + + write_reg_mask(ACPU_SC_VD_CTRL, 0x0, (0x1 << 0) | (0x1 << 11)); + write_reg_mask(PMCTRL_ACPUCLKDIV, 0x1 << 8, 0x3 << 8); + write_reg_mask(PMCTRL_ACPUPLLSEL, 0x1 << 0, 0x1 << 0); + + return 0; +} + +static void acpu_dvfs_clk_div_cfg(unsigned int prof_id, + unsigned int *cpuext_cfg, + unsigned int *acpu_ddr_cfg) +{ + if (0 == prof_id) { + write_reg_mask(PMCTRL_ACPUCLKDIV, + (0x1 << SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_START) | + (0x1 << SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_START), + (0x3 << SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_START) | + (0x3 << SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_START)); + *cpuext_cfg = 0x1; + *acpu_ddr_cfg = 0x1; + } else if (1 == prof_id) { + write_reg_mask(PMCTRL_ACPUCLKDIV, + (0x1 << SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_START) | + (0x1 << SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_START), + (0x3 << SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_START) | + (0x3 << SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_START)); + *cpuext_cfg = 0x1; + *acpu_ddr_cfg = 0x1; + } else { + /* ddr has not been inited */ + write_reg_mask(PMCTRL_ACPUCLKDIV, + (0x1 << SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_START) | + (0x0 << SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_START), + (0x3 << SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_START) | + (0x3 << SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_START)); + *cpuext_cfg = 0x1; + *acpu_ddr_cfg = 0x0; + } + + return; +} + +static int acpu_dvfs_freq_ascend(unsigned int cur_prof, unsigned int tar_prof) +{ + unsigned int reg0 = 0; + unsigned int reg1 = 0; + unsigned int reg2 = 0; + unsigned int count = 0; + unsigned int cpuext_cfg_val = 0; + unsigned int acpu_ddr_cfg_val = 0; + int ret = 0; + + /* + * step 1: + * - PMCTRL_ACPUSYSPLLCFG.acpu_subsys_clk_div_sw = 0x3; + * - ACPUSYSPLLCFG.acpu_syspll_clken_cfg = 0x1; + * + * step 2: + * - PMCTRL_ACPUSYSPLLCFG.acpu_syspll_div_cfg = 0x5 (208MHz) + * - PMCTRL_ACPUSYSPLLCFG.acpu_syspll_div_cfg = 0x2 (500MHz) + * - PMCTRL_ACPUSYSPLLCFG.acpu_syspll_div_cfg = 0x1 (Other OPPs) + * + * step 3: + * - ACPU_SC_CPU_STAT.clk_div_status_vd = 0x3; + * - ACPU_SC_VD_CTRL.tune_en_dif = 0x0; + * - ACPU_SC_VD_CTRL.tune_en_int = 0x0; + * - PMCTRL_ACPUCLKDIV.acpu_ddr_clk_div_cfg = 0x1; + * - PMCTRL_ACPUPLLSEL.acpu_pllsw_cfg = 0x1 + */ + ret = acpu_dvfs_syspll_cfg(cur_prof); + if (ret) + return -1; + + /* + * step 4: + * - Polling PMCTRL_ACPUPLLSEL.syspll_sw_stat == 0x1 + */ + count = 0; + do { + reg0 = read_reg_mask(PMCTRL_ACPUPLLSEL, 0x1, + SOC_PMCTRL_ACPUPLLSEL_syspll_sw_stat_START); + if ((count++) > ACPU_DFS_STATE_CNT) { + ERROR("%s: syspll sw status timeout\n", __func__); + return -1; + } + } while(0x1 != reg0); + + /* Enable VD functionality if > 800MHz */ + if (acpu_dvfs_profile[tar_prof].freq > 800000) { + + write_reg_mask(ACPU_SC_VD_HPM_CTRL, + HPM_OSC_DIV_VAL, HPM_OSC_DIV_MASK); + + /* + * step 5: + * - ACPU_SC_VD_HPM_CTRL.hpm_dly_exp = 0xC7A; + * - ACPU_SC_VD_MASK_PATTERN_CTRL[12:0] = 0xCCB; + */ + write_reg_mask(ACPU_SC_VD_HPM_CTRL, + HPM_DLY_EXP_VAL, HPM_DLY_EXP_MASK); + write_reg_mask(ACPU_SC_VD_MASK_PATTERN_CTRL, + ACPU_SC_VD_MASK_PATTERN_VAL, + ACPU_SC_VD_MASK_PATTERN_MASK); + + /* + * step 6: + * - ACPU_SC_VD_DLY_TABLE0_CTRL = 0x1FFF; + * - ACPU_SC_VD_DLY_TABLE1_CTRL = 0x1FFFFFF; + * - ACPU_SC_VD_DLY_TABLE2_CTRL = 0x7FFFFFFF; + * - ACPU_SC_VD_DLY_FIXED_CTRL = 0x1; + */ + mmio_write_32(ACPU_SC_VD_DLY_TABLE0_CTRL, 0x1FFF); + mmio_write_32(ACPU_SC_VD_DLY_TABLE1_CTRL, 0x1FFFFFF); + mmio_write_32(ACPU_SC_VD_DLY_TABLE2_CTRL, 0x7FFFFFFF); + mmio_write_32(ACPU_SC_VD_DLY_FIXED_CTRL, 0x1); + + /* + * step 7: + * - ACPU_SC_VD_CTRL.shift_table0 = 0x1; + * - ACPU_SC_VD_CTRL.shift_table1 = 0x3; + * - ACPU_SC_VD_CTRL.shift_table2 = 0x5; + * - ACPU_SC_VD_CTRL.shift_table3 = 0x6; + * + * step 8: + * - ACPU_SC_VD_CTRL.tune = 0x7; + */ + write_reg_mask(ACPU_SC_VD_CTRL, + ACPU_SC_VD_SHIFT_TABLE_TUNE_VAL, + ACPU_SC_VD_SHIFT_TABLE_TUNE_MASK); + } + + /* step 9: ACPUPLLCTRL.acpupll_en_cfg = 0x0 */ + write_reg_mask(PMCTRL_ACPUPLLCTRL, 0x0, + 0x1 << SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_START); + + /* step 10: set PMCTRL_ACPUPLLFREQ and PMCTRL_ACPUPLLFRAC */ + mmio_write_32(PMCTRL_ACPUPLLFREQ, + acpu_dvfs_profile[tar_prof].acpu_pll_freq); + mmio_write_32(PMCTRL_ACPUPLLFRAC, + acpu_dvfs_profile[tar_prof].acpu_pll_frac); + + /* + * step 11: + * - wait for 1us; + * - PMCTRL_ACPUPLLCTRL.acpupll_en_cfg = 0x1 + */ + count = 0 ; + while (count < ACPU_WAIT_TIMEOUT) { + count++; + } + write_reg_mask(PMCTRL_ACPUPLLCTRL, + 0x1 << SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_START, + 0x1 << SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_START); + + /* step 12: PMCTRL_ACPUVOLPMUADDR = 0x100da */ + mmio_write_32(PMCTRL_ACPUVOLPMUADDR, 0x100da); + + /* + * step 13: + * - PMCTRL_ACPUDESTVOL.acpu_dest_vol = 0x13 (208MHz); + * - PMCTRL_ACPUDESTVOL.acpu_dest_vol = 0x13 (500MHz); + * - PMCTRL_ACPUDESTVOL.acpu_dest_vol = 0x20 (798MHz); + * - PMCTRL_ACPUDESTVOL.acpu_dest_vol = 0x3A (1300MHz); + * - PMCTRL_ACPUDESTVOL.acpu_dest_vol = 0x3A (1500MHz); + */ + write_reg_mask(PMCTRL_ACPUDESTVOL, + acpu_dvfs_profile[tar_prof].acpu_vol_profile, + ((0x1 << (SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_END + 1)) - 1)); + + /* + * step 14: + * - Polling PMCTRL_ACPUDESTVOL.acpu_vol_using == ACPUDESTVOL.acpu_dest_vol + * - Polling ACPUVOLTIMEOUT.acpu_vol_timeout == 0x1 + * - Config PMCTRL_ACPUCLKDIV.acpu_ddr_clk_div_cfg + * - Config ACPUCLKDIV.cpuext_clk_div_cfg; + */ + count = 0; + do { + reg0 = read_reg_mask(PMCTRL_ACPUDESTVOL, 0x7F, + SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_START); + reg1 = read_reg_mask(PMCTRL_ACPUDESTVOL, 0x7F, + SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_START); + reg2 = read_reg_mask(PMCTRL_ACPUVOLTTIMEOUT, 0x1, + SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_START); + if ((count++) > ACPU_DFS_STATE_CNT) { + ERROR("%s: acpu destvol cfg timeout.\n", __func__); + return -1; + } + } while((reg0 != reg1) || (0x1 != reg2)); + + acpu_dvfs_clk_div_cfg(tar_prof, &cpuext_cfg_val, &acpu_ddr_cfg_val); + + /* + * step 15: + * - Polling PMCTRL_ACPUCLKDIV.cpuext_clk_div_stat; + * - Polling ACPUCLKDIV.acpu_ddr_clk_div_stat; + * - ACPUPLLCTRL.acpupll_timeout = 0x1; + * - PMCTRL_ACPUPLLSEL.acpu_pllsw_cfg = 0x0; + */ + count = 0; + do { + reg0 = read_reg_mask(PMCTRL_ACPUCLKDIV, 0x3, + SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_START); + reg1 = read_reg_mask(PMCTRL_ACPUCLKDIV, 0x3, + SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_START); + reg2 = read_reg_mask(PMCTRL_ACPUPLLCTRL, 0x1, + SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_START); + if ((count++) > ACPU_DFS_STATE_CNT) { + ERROR("%s: acpu clk div cfg timeout.\n", __func__); + return -1; + } + } while((cpuext_cfg_val != reg1) || + (acpu_ddr_cfg_val != reg0) || + (0x1 != reg2)); + + write_reg_mask(PMCTRL_ACPUPLLSEL, 0x0, + 0x1 << SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_START); + + /* + * step 16: + * - Polling PMCTRL_ACPUPLLSEL.acpupll_sw_stat == 0x1; + * - ACPU_SC_VD_CTRL.force_clk_en = 0x0; + * - ACPU_SC_VD_CTRL.clk_dis_cnt_en = 0x0; + * - ACPU_SC_VD_CTRL.calibrate_en_ini = 0x0; + * - ACPU_SC_VD_CTRL.calibrate_en_dif = 0x0; + * - ACPU_SC_VD_CTRL.div_en_dif = 0x1; + * - ACPU_SC_VD_CTRL.tune_en_int = 0x1; + * - ACPU_SC_VD_CTRL.tune_en_dif = 0x1; + * - PMCTRL_ACPUSYSPLLCFG.acpu_subsys_clk_div_sw = 0x0; + * - ACPUSYSPLLCFG.acpu_syspll_clken_cfg = 0x0; + */ + count = 0; + do { + reg0 = read_reg_mask(PMCTRL_ACPUPLLSEL, 0x1, + SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_START); + if ((count++) > ACPU_DFS_STATE_CNT) { + ERROR("%s: acpu pll sw status timeout.\n", __func__); + return -1; + } + } while(0x1 != reg0); + + if (acpu_dvfs_profile[tar_prof].freq > 800000) + write_reg_mask(ACPU_SC_VD_CTRL, + ACPU_SC_VD_EN_ASIC_VAL, ACPU_SC_VD_EN_MASK); + + write_reg_mask(PMCTRL_ACPUSYSPLLCFG, 0x0, + (0x3 << SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_sw_START) | + (0x1 << SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_START)); + + return 0; +} + +static int acpu_dvfs_freq_descend(unsigned int cur_prof, unsigned int tar_prof) +{ + unsigned int reg0 = 0; + unsigned int reg1 = 0; + unsigned int reg2 = 0; + unsigned int count = 0; + unsigned int cpuext_cfg_val = 0; + unsigned int acpu_ddr_cfg_val = 0; + int ret = 0; + + ret = acpu_dvfs_syspll_cfg(tar_prof); + if (ret) + return -1; + + /* + * step 4: + * - Polling PMCTRL_ACPUPLLSEL.syspll_sw_stat == 0x1 + */ + count = 0; + do { + reg0 = read_reg_mask(PMCTRL_ACPUPLLSEL, 0x1, 2); + if ((count++) > ACPU_DFS_STATE_CNT) { + ERROR("%s: syspll sw status timeout.\n", __func__); + return -1; + } + } while(0x1 != reg0); + + /* + * Step 5: + * - PMCTRL_ACPUPLLCTRL.acpupll_en_cfg = 0x0 + */ + write_reg_mask(PMCTRL_ACPUPLLCTRL, 0x0, 0x1 << 0); + + /* + * step 6 + * - Config PMCTRL_ACPUPLLFREQ and ACPUPLLFRAC + */ + mmio_write_32(PMCTRL_ACPUPLLFREQ, acpu_dvfs_profile[tar_prof].acpu_pll_freq); + mmio_write_32(PMCTRL_ACPUPLLFRAC, acpu_dvfs_profile[tar_prof].acpu_pll_frac); + + /* + * step 7: + * - Wait 1us; + * - Config PMCTRL_ACPUPLLCTRL.acpupll_en_cfg = 0x1 + */ + count = 0 ; + while (count < ACPU_WAIT_TIMEOUT) { + count++; + } + + write_reg_mask(PMCTRL_ACPUPLLCTRL, + 0x1 << SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_START, + 0x1 << SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_START); + + /* Enable VD functionality if > 800MHz */ + if (acpu_dvfs_profile[tar_prof].freq > 800000) { + + write_reg_mask(ACPU_SC_VD_HPM_CTRL, + HPM_OSC_DIV_VAL, HPM_OSC_DIV_MASK); + + /* + * step 9: + * - ACPU_SC_VD_HPM_CTRL.hpm_dly_exp = 0xC7A; + * - ACPU_SC_VD_MASK_PATTERN_CTRL[12:0] = 0xCCB; + */ + write_reg_mask(ACPU_SC_VD_HPM_CTRL, + HPM_DLY_EXP_VAL, HPM_DLY_EXP_MASK); + write_reg_mask(ACPU_SC_VD_MASK_PATTERN_CTRL, + ACPU_SC_VD_MASK_PATTERN_VAL, + ACPU_SC_VD_MASK_PATTERN_MASK); + + /* + * step 10: + * - ACPU_SC_VD_DLY_TABLE0_CTRL = 0x1FFF; + * - ACPU_SC_VD_DLY_TABLE1_CTRL = 0x1FFFFFF; + * - ACPU_SC_VD_DLY_TABLE2_CTRL = 0x7FFFFFFF; + * - ACPU_SC_VD_DLY_FIXED_CTRL = 0x1; + */ + mmio_write_32(ACPU_SC_VD_DLY_TABLE0_CTRL, 0x1FFF); + mmio_write_32(ACPU_SC_VD_DLY_TABLE1_CTRL, 0x1FFFFFF); + mmio_write_32(ACPU_SC_VD_DLY_TABLE2_CTRL, 0x7FFFFFFF); + mmio_write_32(ACPU_SC_VD_DLY_FIXED_CTRL, 0x1); + + /* + * step 11: + * - ACPU_SC_VD_CTRL.shift_table0 = 0x1; + * - ACPU_SC_VD_CTRL.shift_table1 = 0x3; + * - ACPU_SC_VD_CTRL.shift_table2 = 0x5; + * - ACPU_SC_VD_CTRL.shift_table3 = 0x6; + * + * step 12: + * - ACPU_SC_VD_CTRL.tune = 0x7; + */ + write_reg_mask(ACPU_SC_VD_CTRL, + ACPU_SC_VD_SHIFT_TABLE_TUNE_VAL, + ACPU_SC_VD_SHIFT_TABLE_TUNE_MASK); + } + + /* + * step 13: + * - Pollig PMCTRL_ACPUPLLCTRL.acpupll_timeout == 0x1; + * - PMCTRL_ACPUPLLSEL.acpu_pllsw_cfg = 0x0; + */ + count = 0; + do { + reg0 = read_reg_mask(PMCTRL_ACPUPLLCTRL, 0x1, + SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_START); + if ((count++) > ACPU_DFS_STATE_CNT) { + ERROR("%s: acpupll timeout.\n", __func__); + return -1; + } + } while(0x1 != reg0); + + write_reg_mask(PMCTRL_ACPUPLLSEL, 0x0, + 0x1 << SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_START); + + /* + * step 14: + * - Polling PMCTRL_ACPUPLLSEL.acpupll_sw_stat == 0x1; + * - ACPU_SC_VD_CTRL.force_clk_en = 0x0; + * - ACPU_SC_VD_CTRL.clk_dis_cnt_en = 0x0; + * - ACPU_SC_VD_CTRL.calibrate_en_ini = 0x0; + * - ACPU_SC_VD_CTRL.calibrate_en_dif = 0x0; + * - ACPU_SC_VD_CTRL.div_en_dif = 0x1; + * - ACPU_SC_VD_CTRL.tune_en_int = 0x1; + * - ACPU_SC_VD_CTRL.tune_en_dif = 0x1; + */ + count = 0; + do { + reg0 = read_reg_mask(PMCTRL_ACPUPLLSEL, 0x1, + SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_START); + if ((count++) > ACPU_DFS_STATE_CNT) { + ERROR("%s: acpupll sw status timeout.\n", __func__); + return -1; + } + } while(0x1 != reg0); + + if (acpu_dvfs_profile[tar_prof].freq > 800000) + write_reg_mask(ACPU_SC_VD_CTRL, + ACPU_SC_VD_EN_ASIC_VAL, ACPU_SC_VD_EN_MASK); + + /* + * step 15: + * - PMCTRL_ACPUSYSPLLCFG.acpu_subsys_clk_div_sw = 0x0; + * - ACPUSYSPLLCFG.acpu_syspll_clken_cfg = 0x0; + */ + write_reg_mask(PMCTRL_ACPUSYSPLLCFG, 0x0, + (0x3 << SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_sw_START) | + (0x1 << SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_START)); + + /* + * step 16: + * - Polling ACPU_SC_CPU_STAT.clk_div_status_vd == 0x0; + */ + count = 0; + do { + reg0 = read_reg_mask(ACPU_SC_CPU_STAT, 0x3, + ACPU_SC_CPU_STAT_CLK_DIV_STATUS_VD_SHIFT); + if ((count++) > ACPU_DFS_STATE_CNT) { + ERROR("%s: clk div status timeout.\n", __func__); + return -1; + } + } while(0x0 != reg0); + + acpu_dvfs_clk_div_cfg(tar_prof, &cpuext_cfg_val, &acpu_ddr_cfg_val); + + /* + * step 17: + * - Polling PMCTRL_ACPUCLKDIV.cpuext_clk_div_stat; + * - Polling ACPUCLKDIV.acpu_ddr_clk_div_stat; + * - PMCTRL_ACPUVOLPMUADDR = 0x1006C; + */ + count = 0; + do { + reg0 = read_reg_mask(PMCTRL_ACPUCLKDIV, 0x3, + SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_START); + reg1 = read_reg_mask(PMCTRL_ACPUCLKDIV, 0x3, + SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_START); + if ((count++) > ACPU_DFS_STATE_CNT) { + ERROR("%s: acpu clk div cfg timeout.\n", __func__); + return -1; + } + } while((cpuext_cfg_val != reg0) || (acpu_ddr_cfg_val != reg1)); + + mmio_write_32(PMCTRL_ACPUVOLPMUADDR, 0x100da); + + /* + * step 16: + * - Polling PMCTRL_ACPUPLLSEL.acpupll_sw_stat == 0x1; + * - ACPU_SC_VD_CTRL.force_clk_en = 0x0; + * - ACPU_SC_VD_CTRL.clk_dis_cnt_en = 0x0; + * - ACPU_SC_VD_CTRL.calibrate_en_ini = 0x0; + * - ACPU_SC_VD_CTRL.calibrate_en_dif = 0x0; + * - ACPU_SC_VD_CTRL.div_en_dif = 0x1; + * - ACPU_SC_VD_CTRL.tune_en_int = 0x1; + * - ACPU_SC_VD_CTRL.tune_en_dif = 0x1; + * - PMCTRL_ACPUSYSPLLCFG.acpu_subsys_clk_div_sw = 0x0; + * - ACPUSYSPLLCFG.acpu_syspll_clken_cfg = 0x0; + */ + write_reg_mask(PMCTRL_ACPUDESTVOL, + acpu_dvfs_profile[tar_prof].acpu_vol_profile, + ((0x1 << (SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_END + 1)) - 1)); + + /* + * step 19: + * - Polling PMCTRL_ACPUDESTVOL.acpu_vol_using == ACPUDESTVOL.acpu_dest_vol + * - ACPUVOLTIMEOUT.acpu_vol_timeout = 0x1; + */ + count = 0; + do { + reg0 = read_reg_mask(PMCTRL_ACPUDESTVOL, 0x7F, + SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_START); + reg1 = read_reg_mask(PMCTRL_ACPUDESTVOL, 0x7F, + SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_START); + reg2 = read_reg_mask(PMCTRL_ACPUVOLTTIMEOUT, 0x1, + SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_START); + if ((count++) > ACPU_DFS_STATE_CNT) { + ERROR("%s: acpu destvol cfg timeout.\n", __func__); + return -1; + } + } while((reg0 != reg1) || (0x1 != reg2)); + + return 0; +} + +int acpu_dvfs_target(unsigned int curr_prof, unsigned int target_prof) +{ + int ret = 0; + + if (curr_prof == target_prof) { + INFO("%s: target_prof is equal curr_prof: is %d!\n", + __func__, curr_prof); + return 0; + } + + if ((curr_prof >= ACPU_FREQ_MAX_NUM) || + (target_prof >= ACPU_FREQ_MAX_NUM)) { + INFO("%s: invalid parameter %d %d\n", + __func__, curr_prof, target_prof); + return -1; + } + + if (target_prof > acpu_dvfs_sram_buf->support_freq_num) + target_prof = acpu_dvfs_sram_buf->support_freq_num; + + if (target_prof < curr_prof) + ret = acpu_dvfs_freq_descend(curr_prof, target_prof); + else if (target_prof > curr_prof) + ret = acpu_dvfs_freq_ascend(curr_prof, target_prof); + + if (ret) { + ERROR("%s: acpu_dvfs_target failed!\n"); + return -1; + } + + /* Complete acpu dvfs setting and set magic number */ + acpu_dvfs_sram_buf->start_prof = target_prof; + acpu_dvfs_sram_buf->magic = ACPU_VALID_VOLTAGE_MAGIC; + + mmio_write_32(DDR_DFS_FREQ_ADDR, 800000); + return 0; +} + +static int acpu_dvfs_set_freq(void) +{ + unsigned int i; + unsigned int curr_prof; + unsigned int target_prof; + unsigned int max_freq = 0; + + max_freq = acpu_dvfs_sram_buf->support_freq_max; + + for (i = 0; i < acpu_dvfs_sram_buf->support_freq_num; i++) { + + if (max_freq == hi6220_acpu_profile[i].freq) { + target_prof = i; + break; + } + } + + if (i == acpu_dvfs_sram_buf->support_freq_num) { + ERROR("%s: cannot found max freq profile\n", __func__); + return -1; + } + + curr_prof = 0; + target_prof = i; + + /* if max freq is 208MHz, do nothing */ + if (curr_prof == target_prof) + return 0; + + if (acpu_dvfs_target(curr_prof, target_prof)) { + ERROR("%s: set acpu freq failed!", __func__); + return -1; + } + + INFO("%s: support freq num is %d\n", + __func__, acpu_dvfs_sram_buf->support_freq_num); + INFO("%s: start prof is 0x%x\n", + __func__, acpu_dvfs_sram_buf->start_prof); + INFO("%s: magic is 0x%x\n", + __func__, acpu_dvfs_sram_buf->magic); + INFO("%s: voltage:\n", __func__); + for (i = 0; i < acpu_dvfs_sram_buf->support_freq_num; i++) + INFO(" - %d: 0x%x\n", i, acpu_dvfs_sram_buf->vol[i]); + + NOTICE("%s: set acpu freq success!", __func__); + return 0; +} + +static void acpu_dvfs_volt_init(void) +{ + /* + * - set default voltage; + * - set pmu address; + * - set voltage up and down step; + * - set voltage stable time; + */ + mmio_write_32(PMCTRL_ACPUDFTVOL, 0x4a); + mmio_write_32(PMCTRL_ACPUVOLPMUADDR, 0xda); + mmio_write_32(PMCTRL_ACPUVOLUPSTEP, 0x1); + mmio_write_32(PMCTRL_ACPUVOLDNSTEP, 0x1); + mmio_write_32(PMCTRL_ACPUPMUVOLUPTIME, 0x60); + mmio_write_32(PMCTRL_ACPUPMUVOLDNTIME, 0x60); + mmio_write_32(PMCTRL_ACPUCLKOFFCFG, 0x1000); + + INFO("%s: success!\n", __func__); +} + +void init_acpu_dvfs(void) +{ + unsigned int i = 0; + + INFO("%s: pmic version %d\n", __func__, hi6553_read_8(VERSION_REG)); + + /* init parameters */ + mmio_write_32(ACPU_CHIP_MAX_FREQ, efuse_acpu_freq[8]); + INFO("%s: ACPU_CHIP_MAX_FREQ=0x%x.\n", + __func__, mmio_read_32(ACPU_CHIP_MAX_FREQ)); + + /* set maximum support frequency to 1.2GHz */ + for(i = 0; i < ACPU_FREQ_MAX_NUM; i++) + acpu_dvfs_sram_buf->vol[i] = hi6220_acpu_profile[i].acpu_vol_profile; + + acpu_dvfs_sram_buf->support_freq_num = ACPU_FREQ_MAX_NUM; + acpu_dvfs_sram_buf->support_freq_max = 1200000; + + /* init acpu dvfs */ + acpu_dvfs_volt_init(); + acpu_dvfs_set_freq(); + + return; +}
Signed-off-by: Leo Yan leo.yan@linaro.org --- plat/hikey/platform.mk | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/plat/hikey/platform.mk b/plat/hikey/platform.mk index 9eabbc6..8fc64f1 100644 --- a/plat/hikey/platform.mk +++ b/plat/hikey/platform.mk @@ -66,6 +66,8 @@ BL1_SOURCES += drivers/arm/cci400/cci400.c \ plat/hikey/aarch64/bl1_plat_helpers.S \ plat/hikey/bl1_plat_setup.c \ plat/hikey/drivers/dw_mmc.c \ + plat/hikey/drivers/hisi_adc.c \ + plat/hikey/drivers/hisi_dvfs.c \ plat/hikey/drivers/hi6553.c \ plat/hikey/drivers/sp804_timer.c \ plat/hikey/partitions.c \ @@ -75,6 +77,7 @@ BL1_SOURCES += drivers/arm/cci400/cci400.c \ BL2_SOURCES += plat/common/aarch64/platform_up_stack.S \ plat/hikey/bl2_plat_setup.c \ plat/hikey/drivers/dw_mmc.c \ + plat/hikey/drivers/hisi_mcu.c \ plat/hikey/drivers/sp804_timer.c \ plat/hikey/partitions.c
Signed-off-by: Leo Yan leo.yan@linaro.org --- plat/hikey/pll.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/plat/hikey/pll.c b/plat/hikey/pll.c index 20f7a5a..ed007b9 100644 --- a/plat/hikey/pll.c +++ b/plat/hikey/pll.c @@ -45,7 +45,6 @@ static void init_pll(void) { unsigned int data;
- data = mmio_read_32((0xf7032000 + 0x000)); data |= 0x1; mmio_write_32((0xf7032000 + 0x000), data); @@ -54,7 +53,6 @@ static void init_pll(void) data = mmio_read_32((0xf7032000 + 0x000)); } while (!(data & (1 << 28)));
- data = mmio_read_32((0xf7800000 + 0x000)); data &= ~0x007; data |= 0x004; @@ -1061,17 +1059,17 @@ static void reset_mmc0_clk(void) unsigned int data;
/* disable mmc0 bus clock */ - mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK_MMC0); + mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); do { data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); - } while (data & PERI_CLK_MMC0); + } while (data & PERI_CLK0_MMC0); /* enable mmc0 bus clock */ - mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK_MMC0); + mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); do { data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); - } while (!(data & PERI_CLK_MMC0)); + } while (!(data & PERI_CLK0_MMC0)); /* reset mmc0 clock domain */ - mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_CLK_MMC0); + mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0);
/* bypass mmc0 clock phase */ data = mmio_read_32(PERI_SC_PERIPH_CTRL2); @@ -1115,7 +1113,10 @@ static void init_media_clk(void)
void hi6220_pll_init(void) { + init_hkadc(); + init_boardid(); init_pll(); + init_acpu_dvfs(); init_freq(); init_ddr(); init_ddrc_qos();
-
Leo Yan -
Rob Herring -
Victor Chong